On 2/6/15 12:42 PM, Hal Murray wrote:
mag...@rubidium.dyndns.org said:
The typical noise generator chips uses a PRNG based on DFFs and XOR
gate(s). A typical weakness is that the chain of DFFs is to short, causing
a relatively high rate of cycling, which hearable as a beating. However, for
some uses, that is OK.
The buzzword for the typical PRNG is LFSR - Linear Feedback Shift Register.
Many years ago, Xilinx published a good app-note on this topic. There is
also a section in Art of Electronics.
With the right generating polynomial, you get a sequence of bits that doesn't
repeat until 2^N-1 bits. The math geeks like to collect them. Each 1 bit in
the polynomial turns into an XOR gate, so you will also find collections of
polynomials with fewest bits.
Only "maximal" codes have 2^n-1 states/periods. There are other
configurations with shorter periods. A particularly tricky thing is
that if the shift register in a maximal generator ever winds up as all
zeros (e.g. from a upset or bit flip), then the generator sticks at
zero. All maximal generators have an even number of taps, too.
You can do all kinds of interesting things considering the generator as
a polynomial (like factoring)
The Spread Spectrum Systems book by Dixon describes lots of ways to make
fast generators. The usual vanilla design shows all the taps going to a
big modulo 2 adder, but it's more efficient to put an xor between each
flip flop, and run the feedback to those stages that have taps. In fact,
clever design integrates the XOR into the flipflop logic, so you can
basically clock the PN generator at the toggle rate of the flip flops.
There are also a plethora of schemes using multiple generators running
in parallel with the outputs XORed.. Gold and Kasami codes are good
examples where the two generators run at the same rate. GPS C/A and
P(Y) code is an example where the generators run at different rates.
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