On Sun, 10 Jan 2016 14:30:41 +0100 Magnus Danielson <mag...@rubidium.dyndns.org> wrote:
> > SR-flipflop? Are you refering to the JK-FF phase detector or the PFD? > > A straight SR-flipflop. I would have written JK-FF or PFD if I meant it. > Also, as I mentioned the PFD directly after, you could have concluded > that was not what I intended. > > A SR-flip-flop with no illegal input states is easy to build from a 74HC00. The illegal input states were my concern, indeed. And a quick google didn't show up anything to disperse these....not until I started reading the 4046 datasheet in detail. But there is one thing about the arangement of the SR FF in the 4046[1] that bothers me: Although S = R = 1 is valid, it does lead to the output oscillating between 0 and 1. Attila Kinali [1] Ti CD74HC4046A Datasheet http://www.ti.com/lit/ds/symlink/cd54hc4046a.pdf -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.