I was thinking to make a frequency divider by using FPGA. Here is my
attempt to implement it using VHDL.
This is frequency divder plus D flip-flop which I was planed to use as
source of 60Hz for my Telechron clock.
However I never implement it in HW. Instead I was using STM32F4 with its
timers.
The purpose was to divide 9.8304 Mhz OCXO output by 81920 to get 60Hz
and use the D flip-flop to keep output in sync.
Some day I'll return to this with my soldering iron in hands. ;-)
----------------------------------------------------------------------------------
-- Company:
-- Engineer: V.P.
--
-- Create Date: 17:58:43 11/09/2015
-- Design Name:
-- Module Name: freq_div - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity freq_div is
Port ( clk_in : in STD_LOGIC;
rst : in STD_LOGIC;
clk_out : out STD_LOGIC);
end freq_div;
architecture Behavioral1 of freq_div is
signal prescaler : integer range 0 to 81919 :=0;
signal clk_out_i : std_logic;
begin
gen_clk : process (clk_in, rst)
begin -- process gen_clk
if rst = '1' then
clk_out_i <= '0';
prescaler <= 0;
elsif rising_edge(clk_in) then -- rising clock edge
if (prescaler = 81919) then
prescaler <= 0;
clk_out_i <= not clk_out_i;
else
prescaler <= prescaler + 1;
end if;
end if;
end process gen_clk;
clk_out <= clk_out_i;
end Behavioral1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
Port ( d_clk_in : in STD_LOGIC;
d_rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC
);
end d_ff;
architecture Behavioral2 of d_ff is
begin
d_ff_clk : process (d_clk_in, d_rst, D)
begin -- process d_ff_clk
if ( rising_edge(d_clk_in) ) then --This makes the process
synchronous(with clock)
if(d_rst = '1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process; --end of process statement.
end Behavioral2;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity Z1 is
Port ( z1in : in STD_LOGIC; -- clk_in
z2in : in STD_LOGIC; -- reset
z1out : out STD_LOGIC -- Signal Out
);
end Z1;
architecture SOut of Z1 is
component freq_div is
Port ( clk_in : in STD_LOGIC;
rst : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component;
component d_ff is
Port ( d_clk_in : in STD_LOGIC;
d_rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
signal wire: std_logic; -- put signal to "wire" or use it as a "wire"
begin
u0:
freq_div
port map (
clk_in => z1in,
rst => z2in,
clk_out => wire
);
u1:
d_ff
port map (
d_clk_in => z1in,
d_rst => z2in,
D => wire,
Q => z1out
);
end SOut;
On 2016-01-13 21:35, Nick Sayer via time-nuts wrote:
The code is at
https://github.com/nsayer/GPS-disciplined-OXCO/blob/master/tiny_divider.c
It’s a first cut. The code at the moment will just divide the input
clock by 10 million, so you get a 1 PPS 50% duty square wave out. It
should run on any ATTinyx5 model - it certainly will fit on at
ATTiny25 if you wish.
I’ve not exhaustively tested it yet. I need to feed it into my TIA
to make sure it’s exactly 1 Hz - it’s conceivable I’ve committed
a fencepost error that would make it off enough that my scope can’t
tell (my TIA is busy at the moment).
I believe the code won’t do the math properly below 10 MHz. You’d
need to select the next lower prescale setting and change a couple of
the formulae, but I don’t foresee an issue with doing so.
I’ll come back with an exhaustive test report (and any bug fixes)
when I get my TIA back from GPSDO ADEV duty. :)
On Jan 13, 2016, at 12:12 PM, Nick Sayer <nsa...@kfu.com> wrote:
Just shy of a half dozen folks have asked, so I'll post here as soon
as I finish cleaning it up. I'll put it on Github when it's ready. I
just need a day or two.
Sent from my iPhone
On Jan 13, 2016, at 6:43 AM, Nick Sayer via time-nuts
<time-nuts@febo.com> wrote:
If anyone is interested in the equivalent functionality using an
ATTiny25 (for instance, if you’re already heavily invested in AVR
instead of PIC, like I am), ping me. I’ve privately written code to
solve almost the same problem and it could easily be adapted into
doing the same job.
On Jan 13, 2016, at 5:23 AM, Edesio Costa e Silva
<time-n...@tardis.net.br> wrote:
Hi!
Try TVB's picDiv at http://www.leapsecond.com/pic/picdiv.htm
Edésio
On Wed, Jan 13, 2016 at 09:22:09AM +0000, Jerome Blaha wrote:
Hey Guys,
Is there an easy circuit to build that can consistently deliver a 1
PPS from a 10MHz source with excellent resolution and
repeatability? My first application is to test different 10MHz
oscillators without a TIC always attached and then compare the PPS
output change over time against a master GPSDO PPS with an
HP53132A.
The circuit used for PPS generation would have to deliver
consistent PPS output with preferably not more than 100ps noise or
jitter, assuming a perfect source. I'm totally guessing that for
this resolution, the PPS would have to be generated and accurate to
within 0.001Hz every second. If this is too difficult, maybe the
integration time can be increased to generate one pulse every
10second or every 100,000,000.00 cycles?
Finally, is a square 10Mhz reference any better in this case than a
sinusoidal input for generating the PPS?
Thanks,
Jerome
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--
WBW,
V.P.
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