On Thu, 14 Jan 2016 09:50:15 -0500 Vlad <t...@patoka.org> wrote: > I was thinking to make a frequency divider by using FPGA. Here is my > attempt to implement it using VHDL. > This is frequency divder plus D flip-flop which I was planed to use as > source of 60Hz for my Telechron clock. > However I never implement it in HW. Instead I was using STM32F4 with its > timers. > The purpose was to divide 9.8304 Mhz OCXO output by 81920 to get 60Hz > and use the D flip-flop to keep output in sync. > Some day I'll return to this with my soldering iron in hands. ;-)
Nice! As side note: when using an FPGA anyways, it might be good to use something like a lambda divider [1,2]. I'm not so sure whether their explanation why this improves the noise floor is the right one, but it definitly helps and is quite easy to implement. Attila Kinali [1] " The sampling theorem in Pi and Lambda dividers", by Calosso, Rubiola, 2013 http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf [2] Slides to the above http://rubiola.org/pdf-slides/2013C-IFCS--Dividers.pdf -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.