On Mon, 18 Jan 2016 14:34:56 -0500 Bob Camp <kb...@n1k.org> wrote: > The nice thing about a FPGA (or CPLD) is that they come with a cute timing > analyzer. You can indeed > answer questions like this with a quite high level of confidence. That > *assumes* that you bother to set > up the timing analyzer :)
I wouldn't trust that timing analyzer too much. We just build a TDC using an Cyclone 4 FPGA here (actually, porting the OHWR delay line TDC from Spartan to Cyclone) and the timing analysis was... weird, at best. Although the average delay was about right (40ps and 120ps) it only showed a two element structure, ie the delays of the chain were "40ps, 120ps, 40ps, 120ps,..." without any higher level structure (which should have shown). The test results showed a quite more detailed structure with few delays over 100ps and most being between 20ps and 80ps. Interestingly, some were close to 0ps, for which we have no explanation good explanation. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.