Am Mon, 18 Apr 2016 18:15:22 -0400 schrieb Bob Camp <kb...@n1k.org>: > Hi > > If our approach was to fabricate an IC totally from scratch for this > or that application, there are a lot of things that could be done. > Unfortunately, for most of us, doing that to wire up an output on a > board … not so much. > I fully agree, usually this is totally out of question. But, IF one does need something like that, AND has the proper tools/skills available, this would be feasible at not so high cost. Having Skills and tools available does not necessarily mean to personally have these. Quite a number of university groups do work on IC design of some sort. Where I work, we regularly do MPW runs for all sorts of customers, among which are quite a number of universities. In our basic 250nm process, MPW goes at slightly less than 3k Euro per square millimetre for up to 40 parts. One square millimetre does get you quite far in 250nm technologies. Sure, this does not include packaging as we don't do that. And yes, one can easily get plain CMOS for much less than that elsewhere. But for that sort of money you'd actually get a full SiGe BiCMOS process. No, I definitely wouldn't recommend that sort of pricing for production of millions of pieces a year, but that's not our main target in any case, as we're a research institution, not a commercial foundry. Plain 250nm CMOS through educational outfits like europractice or MOSIS, I'd expect to run at about half to one third that price.
> Starting back in the 1970’s people stopped making packaged inverters > with single transistor pairs. The problem was they didn’t get enough > gain or isolation through a single pair. For the few places that > *did* keep making the single pair parts, they carefully labeled them > as such so you would not misuse them. > > Once you get into packaged logic designed in the 80’s or later, > “unbuffered” gates pretty much vanish. An inverter is made of three > transistor pairs and a “non inverter” is made from two transistor > pairs. The net result is that the “non inverter” is slightly faster. > Again, this does not apply if you make your own chip from scratch on > a silicon wafer. It only applies if you want to buy pre-packaged > parts from somebody like TI. > > The speed difference is not as great as you might think. The > capacitance on the internal nodes is mighty low. That makes the > “internal” inverter very fast compared to the rest of the circuit. > I'd consider something on the order of 100 ps of gate delay per stage. But this strongly depends on load. In "standard" 250 nm CMOS with about 5 nm Gate Oxide, gate capacitance is on the order of 50fF/um^2, so a single minimum drive strength inverter would be slightly more than 10fF. Agreed, that's not very much. As a matter of fact, I myself would ignore it at PCB level. But with transistor saturation currents on the order of 100uA, it'll take some time to charge and discharge... And If you're trying to meet JEDEC standards for CMOS drive strength, you'll end up with transistors of a hundred microns gate width or more, which by themselves already pose a significant capacitive load on the order of a few picofarads. Well, insignificant in most PCB environments, but on chip this is pretty significant. And when one needs to go from core logic (about one micron gate width, 10-30 fF capacitance, max current 100uA) to PCB (capacitive loads of tens of picofarads, several milliamps of current drive at low voltage drops), the optimization isn't that straightforward: a high number of stages with low relative capacitive load (meaning that one stage has a low multiple of its own input capacitance as a load on its output) might or might not be preferred over a low number of stages, where each one sees huge relative capacitive loads and therefore has long transition times. In the end it's a tradeoff between Input-to-Output delay, risetime and power consumption. But certainly a higher number of stages does not necessarily mean higher input-to-output delay. > Of course if you *did* fabricate a single transistor pair on your > own, you also would need to invent a way to dice it so that pair was > not “swimming” in an ocean of un-used silicon. The capacitance of all > that real estate counts as well … > Oh yeah. A single inverter would need something on the order of maybe 2umx5um.Compared to that, even a single bond pad would be really huge with 80um x 80um. And one would need at least four bond pads. If one needs to add proper ESD protection, we'll get to something like 300um x 300um, which is about the smallest we could actually reliably dice out of an 8 inch wafer. But hold your breath while handling ;-) But, in the case you mentioned, one would try and get away from the silicon as soon as possible, up the layer stack. And then capacitance to the silicon bulk is no longer that much of a problem as the distance between conductor and silicon is increased roughly by a factor of thousand. In case this still is too much, one could do some clever processing as well, etching away most of the silicon bulk and refilling with oxide and thereby further decrease capacitance at the expense of a more complex process and poor thermal properties. But if needs be, it can be done. > Lots of Fun. > Definitely. Florian _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.