Hi What sort of phase noise levels are you trying to measure? If you are after -80 dbc/Hz sort of numbers, there are a lot of ways to do the job. For low noise stuff (-160 dbc/ Hz) the quickest way to do it is a mixer / two oscillators in quadrature and a sound card. The “pure digital” equivalent of that is an XOR gate running into a sound card. The XOR is not as quiet as a proper mixer. The “detector” (ADC / mixer / XOR) is what sets the noise floor and limits measurement capabilities of the device.
Bob > On Jun 12, 2016, at 11:50 PM, John Swenson <johnswens...@comcast.net> wrote: > > Hi TimeNuts, this is my first post to this list, I've been reading it for > years but haven't needed to post, now I'm starting a project and need some > advice. > > I need to do a bunch of phase noise measurements but can't afford the "big > guys", the TimePod seems perfect and since the schematic has been published I > decided I would try my hand at making my own version. > > I'm just doing phase noise measurements of digital clocks (square waves) so > it seems to me I don't need some of the circuitry in the TimePod, in > particular the digitally controlled RF attenuators and the ADCs themselves. > My idea is to use LVPECL flip-flops to sample the DUT and reference clocks, > convert the differential outputs to CMOS and feed the FPGA inputs from that. > Yes you loose AM noise riding on top of the square wave, but is that really > necessary for just square wave phase noise measurements? > > For a first pass cheap and dirty version of this I was planning on using the > LVPECL version of the Crystek 575 for the sample clock, will this work? The > TimePod schematic shows a VTUNE signal fed to the OCXO, if I don't use that > is something going to break? In other words will timelab try and tweak the > sample freaquency and get confused when nothing happens? > > I plan on using the 2 reference clock measurement technique, but have a > couple questions about this. In the TimePod ch 0 and 2 are the input, with > separate jacks available. The "ref" input goes to ch 1 and 3. So it looks > like the two references have to go to 0 and 2 and the DUT to 1 and 3, even > though that puts the references on the "input" and the DUT on the > "reference". Do you need to do anything special in TimeLab to support this or > does it automatically support it? Since I am doing my own hardware and have > four independent inputs do I do the same thing (ref clocks on 0 and 2 and DUT > on 1 and 3) or put the refs on 1 and 3 and the DUT on 0 and 2? > > Any thoughts? > > Thanks, > > John S. > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
