Is there a schematic showing what you attempted? I went back through the discussion thread and it was not real clear to me which design you implemented.
On Mon, 26 Sep 2016 21:18:25 -0700, you wrote: >... > >The results arent very good. > >With a short TC loop filter, the PLL does lock up, but obviously the jitter of >the Venus 10 MHz output comes through. > >With a longer TC, the PLL never locks - or at least if it does lock, its >locking significantly off frequency. > >Thats with a 10 µF cap and varied resistors between 10k and 1M. The best I >got was at 200k - a TC of 2s. That resulted in this video. Unlike other videos >Ive made comparing two GPSDOs, this one is not a time-lapse. The reference is >an OH300 based GPSDO. > >https://www.youtube.com/watch?v=hiHRp0dCJ64 ><https://www.youtube.com/watch?v=hiHRp0dCJ64> > >A time constant of 10s (1M resistor) just doesnt work at all. > >But the real nail in the coffin here is that the price of the PLL chip is >still more expensive than the microcontroller and all of the components it >replaces. > >... _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
