-------- In message <20161029134952.e60a2182e1f53844ec50b...@kinali.ch>, Attila Kinali writes:
>> nsa...@kfu.com said: >> > That single-chip version is going to have a *LOT* less (and less variable) >> > latency than an SDR. >> >> Latency isn't an issue as long as it is known so that you can correct for it. >> >> Has anybody measured the jitter through SDR and/or tried to reduce it? I'd >> expect that even if you counted cycles and such there would still be jitter >> from not being able to reproduce cache misses and interrupts. > >Should not be too high. It should be nonexistent. The sensible way to do SDR-timing, is to capture a signal from the disciplined oscillator with the ADC samples, so that their precise timing relationship is firmly bolted down. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
