kb...@n1k.org said: > You have a âgateâ from the GPSDO and a âsignalâ from somewhere else. > If you > want the STM to do the whole thing, the âgateâ pin needs to get the job > done > in X +/- 1 cycles of the âsignalâ pin. Delay X (if itâs consistent) > isnât > a problem. Having a > +/- 1 cycle delay *is* a problem. The interrupt servicing structure in the > MCU may or may not be able to hit things +/- 10 ns or even +/- 100 ns. > Sometimes a âlower powerâ MCU with simple code is better at this than a > multi core gizmo running a high level operating system.
Some of the counter/timer hardware has another register where the hardware will save a copy of the main counter when another signal happens. If your gate time is the time between two pulses rather than the width of a single pulse, then all the software has to do is read that copy-register before the next pulse happens. -- These are my opinions. I hate spam.
_______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.