On Thu, September 7, 2017 10:56 am, Mark Sims wrote: > It takes a 10 MHz input, feeds it through a sine-to square converter > (using a biased CMOS gate) doubles it to 20 MHz using XOR gates,
Could you send me a snip of what that looks like? Or a link to the schematic if you have it already. I need to take 10MHz in and was going to generate 24MHz with a PLL, but probably 20MHz will be acceptable, and I think just a couple of gates would work a lot better from a space and power layout perspective. If I need 50/50 duty cycle I would need to double again to 40MHz and use a flip-flop to divide by 2, right? Does the XOR circuit still work OK with a narrow duty cycle? thanks, Chris Caudle _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.