On 4/11/18 3:00 AM, Pete Lancashire wrote:
Needed for SDR project as external clock source.
-pete
I assume you mean derived from a high quality 10 MHz.
some sort of discrete divide multiply? divide by 5 multiply by 12?
A PLL with VCXO with good far out noise? (sort of like "clean up loops"
used for distributing 10 or 100 MHz )
A DDS (with internal multiplier)
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