Hi all,
I've written a couple of BDI2000 .cfg files, with
register settings consistent with the latest
U-Boot source. I've tested it on both the
Freescale boards:
MPC8349E-MDS-PB:
- MPC8349E processor (v1.x silicon)
- DDR1 SDRAM
- Micron Q-Flash
MPC8349EA-MDS-PB:
- MPC8349EA processor (v3.x silicon)
- DDR2 SDRAM
- Spansion Flash
Wolfgang/Stefan could you place these in the
ftp://www.denx.de/pub/BDI2000, as they may be
useful to others.
I'll send the two files separately to avoid
the newsgroup file size limits.
[1/2] BDI .cfg for MPC8349E-MDS-PB
Thanks!
Dave
; bdiGDB configuration file for MPC8349E-MDS-PB board
;------------------------------------------------------------------
;
; 3/03/2008 D. W. Hawkins ([EMAIL PROTECTED])
;
; The Freescale MPC8349E/EA PowerQUICC II PowerPC processor
; has two evaluation boards;
;
; * MPC8349E-MDS-PB
; - MPC8349E processor (v1.x silicon)
; - DDR1 memory
; - Micron Q-Flash.
;
; * MPC8349EA-MDS-PB
; - MPC8349EA processor (v3.x silicon)
; - DDR2 memory
; - Spansion Mirror-bit (S29GL) Flash.
;
; The DDR memory controller requires a different configuration
; for the two boards, and the programming algorithms for the
; Flash is different.
;
;------------------------------------------------------------------
; NOTES:
; ------
;
; 1. If the DDR memory is not known to be working (eg. on another
; MPC8349EA-based board), comment out the WORKSPACE used by
; the [FLASH] programming section below.
;
; 2. The memory map (local address window LAW) register settings
; in the [INIT] section were made identical to the
; U-Boot 1.3.1 settings (read from the board registers
; after U-Boot had started).
;
; 0x0000_0000 - 0x0FFF_FFFF 256MB DDR1 (single SODIMM)
; 0xE000_0000 - 0xE00F_FFFF 1MB IMMR
; 0xE240_0000 - 0xE240_7FFF 32kB BCSR
; 0xFE00_0000 - 0xFFFF_FFFF 32MB Flash
;
; Note that the BCSRs are located at 0xF800_0000 in the
; Freescale MPC8349E-MDS-PB documentation. That documentation
; also defines PCI inbound/outbound windows. These windows
; are not configured by this configuration file, or by
; U-Boot 1.3.1.
;
; 3. U-Boot 1.3.1 uses low-memory boot, i.e., BMS = 0 in the
; reset configuration words. The DIP switch for FCFG
; (SW4.8) must be in the '1' position (closest to the
; power connector below it). This ensures that the RCWs
; are read from Flash.
;
; Once the Flash is programmed, the RCW entry in the
; [TARGET] section can be commented out.
;
; 4. U-Boot 1.3.1 initial messages:
;
; CPU: e300c1, MPC8349E, Rev: 11 at 528 MHz, CSB: 264 MHz
; Board: Freescale MPC8349EMDS
; I2C: ready
; DRAM: 256 MB (DDR1, 64-bit, ECC off)
; FLASH: 8 MB
; In: serial
; Out: serial
; Err: serial
; Net: TSEC0, TSEC1
;
; So the CPU operates at 528MHz, the DDR operates
; at 132MHz clock rate (264MHz data rate), DDR ECC is off.
;
; 5. There are DDR registers defined in the MPC8349EA reference
; manual, that are not supposed to be programmed on the
; MPC8349E. AN3055 lists most of the register differences [5].
;
; The following registers are programmed in the
; mpc8349ea_mds_pb.cfg file, but they are not used in the
; mpc8349e_mds_pb.cfg file (this file):
;
; Register offset relative to IMMR:
; - 0x0128 DDRCDR
; - 0x2100 TIMING_CFG_3
; - 0x2104 TIMING_CFG_0
; - 0x2114 DDR_SDRAM_CFG_2
; - 0x211C DDR_SDRAM_MODE_2
;
;------------------------------------------------------------------
; REFERENCES:
; -----------
;
; [1] "MPC8349E PowerQUICC II Pro Integrated Host Processor
; Family Reference Manual", Rev. 1 8/2005, Freescale
; Semiconductor (MPC8349ERM.pdf).
;
; *** WARNING ***
; There was a revision 2 version of this manual released,
; however, that manual became the MPC8349EA manual, and
; the MPC8349E manual reverted to revision 1.
;
; [1b] "Errata to the MPC8349E PowerQUICC II Pro Integrated Host
; Processor Family Reference Manual, Rev. 1", Rev 1.2,
; 08/2006 (MPC8349ERMAD.pdf).
;
; [2] "MPC8349E MDS Processor Board User Manual", Rev. 1.6,
; 12/2005, Freescale Semiconductor.
;
; [3] "MT46V64M4, MT46V32M8, MT46V16M16: 256Mb x4 x8 x16 DDR SDRAM"
; Micron Technologies, 2000 (256MBDDRx4x8x16.pdf)
;
; [4] "MT28F128J3, MT28F640J3, MT28F320J3: 128Mb, 64Mb, 32Mb
; Q-Flash memory", Micron Technologies, 2004 (MT28F640.pdf)
;
; [5] "AN3055: Migration from MPC834x Revision 1.x to Revision
; 3.x", Freescale, Rev 4, 1/2008
;
;------------------------------------------------------------------
;
; =================================================================
[INIT]
; init core register
WREG MSR 0x00001002 ;MSR : ME,RI
; Internal Memory Mapped Registers (IMMR)
; ---------------------------------------
;
; The base address of the 1MB of IMMR registers defaults
; to 0xFF40_0000 (see Ch. 2 and Ch. 5 [1]).
;
; Write to IMMRBAR to move the IMMRs to 0xE000_0000.
;
WM32 0xFF400000 0xE0000000
; Local Address Windows (LAWs)
; ----------------------------
;
; The processor has 9 LAWs (see Table 5-1 in Ch. 5 [1]).
;
; The MPC8349E-MDS-PB uses;
; - a local-bus LAW for Flash
; - a local-bus LAW for BCSRs
; - a DDR LAW for DDR1 memory
; - and it can use a PCI LAW for PCI accesses
;
; Local-bus Flash
; ---------------
; LBC Local Access Window 0 Base Address Register (p5-8 [1]).
; LBLAWBAR0
; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned)
; [20:31] ----- Reserved
;
; LBC Local Access Window 0 Attributes Register (p5-9 [1]).
; LBLAWAR0
; [0] EN Enabled (1)
; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes
;
WM32 0xE0000020 0xFE000000 ;LBLAWBAR0 Flash
WM32 0xE0000024 0x80000016 ;LBLAWAR0 8MB
; Local-bus Board Control and Status Registers (BCSRs)
; ----------------------------------------------------
; LBC Local Access Window 1 Base Address Register (p5-8 [1]).
; LBLAWBAR1
; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned)
; [20:31] ----- Reserved
;
; LBC Local Access Window 1 Attributes Register (p5-9 [1]).
; LBLAWAR1
; [0] EN Enabled (1)
; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes
;
WM32 0xE0000028 0xE2400000 ;LBLAWBAR1 BCSR
WM32 0xE000002C 0x8000000E ;LBLAWAR1 32kB
; DDR Memory
; ----------
; DDR Local Access Window 0 Base Address Register (p5-12 [1]).
; DDRLAWBAR0
; [ 0:19] BASE_ADDR Base address MSBs (1MB aligned)
; [20:31] ----- Reserved
;
; DDR Local Access Window 0 Attributes Register (p5-13 [1]).
; DDRLAWAR0
; [0] EN Enabled (1)
; [26:31] SIZE Decode region is 2^(SIZE-1)-bytes
;
WM32 0xE00000A0 0x00000000 ;DDRLAWBAR0 SODIMM#1
WM32 0xE00000A4 0x8000001B ;DDRLAWAR0 256MB
; DDR Clock Control
; -----------------
;
; MCK Enable Register (p4-46 [1], and p4 of the errata [1b])
; MCKENR
; [0] CE0 MCK[0]/MCK#[0] disable(0) / enable (1)
; [1] CE1 MCK[1]/MCK#[1] disable(0) / enable (1)
; [2] CE2 MCK[2]/MCK#[2] disable(0) / enable (1)
; [3] CE3 MCK[3]/MCK#[3] disable(0) / enable (1)
; [4] CE4 MCK[4]/MCK#[4] disable(0) / enable (1)
; [5] CE5 MCK[5]/MCK#[5] disable(0) / enable (1)
;
; The reset value for this register is 0xFC00_0000,
; i.e., all clocks enabled. The schematic shows that
; all the clock are used, so this default is appropriate.
; Note that the second SODIMM is not populated, so
; CK[0:2] could be disabled.
;
;WM32 0xE0001010 0xFC000000 ;MCKENR
; DDR Clock Control (p9-17 [1])
; -----------------
; DDR_SDRAM_CLK_CNTL
; [0: 4] ---- Reserved
; [5: 7] CLK_ADJUST Clock adjust
; [8:31] ---- Reserved
;
; CLK_ADJUST resets to 000b, so the clock is launched aligned
; with the address/command. This should be changed to 010b
; so that the clock is launched 1/2 clock after address/command.
;
WM32 0xE0002130 0x02000000 ;DDR_SDRAM_CLK_CNTL
; DDR Memory Controller
; ---------------------
;
; Chip-select n (0,1,2,3) memory bounds (p9-10 [1])
; CSn_BNDS
; [ 0: 7] --- Reserved
; [ 8:15] SAn Start address for bank n
; [16:23] --- Reserved
; [24:31] EAn Start address for bank n
;
; The MPC8349E-MDS-PB connects the four chip-selects
; (CS#[0:3]) to the two SODIMM modules. Only one SODIMM
; is populated by default (U543), so only the two chip
; selects used by that SODIMM need to be configured,
; i.e., CS#[2:3].
;
; Configure for;
; - CS#[2] memory range: 0x0000_0000 - 0x07FF_FFFF
; Start/end addresses (8-MSBs of the 32-bit memory addresses)
; SA = 0x00, EA = 0x07
; - CS#[3] memory range: 0x0080_0000 - 0x0FFF_FFFF
; SA = 0x08, EA = 0x0F
;
WM32 0xE0002000 0x00000000 ;CS0_BNDS
WM32 0xE0002008 0x00000000 ;CS1_BNDS
WM32 0xE0002010 0x00000007 ;CS2_BNDS
WM32 0xE0002018 0x0008000F ;CS3_BNDS
; Chip-select n (0,1,2,3) configuration (p9-10 [1])
; CSn_CONFIG
; [0] CS_n_EN Chip-select enable
; [ 1: 7] ---- Reserved
; [8] AP_n_EN Auto-precharge enable
; [ 9:20] ---- Reserved
; [21:23] ROW_BITS_CS_n Number of row bits
; [24:28] ---- Reserved
; [29:31] COL_BITS_CS_n Number of column bits
;
; Configure for;
; - CS#[0, 1] disabled
; - CS#[2, 3] configure for;
; CS_n_EN = 1b Enabled
; AP_n_EN = 0b Use global auto-precharge control
; ROW_BITS_CS_n = 001b 13 row bits
; COL_BITS_CS_n = 001b 9 column bits
;
WM32 0xE0002080 0x00000000 ;CS0_CONFIG
WM32 0xE0002084 0x00000000 ;CS1_CONFIG
WM32 0xE0002088 0x80000101 ;CS2_CONFIG
WM32 0xE000208C 0x80000101 ;CS3_CONFIG
; TIMING_CFG_1 (p9-11 [1])
; [0] ---- Reserved (should be 0)
; [ 1: 3] PRETOACT Precharge-to-activate
; [ 4: 7] ACTTOPRE Activate to precharge
; [8] ---- Reserved (should be 0)
; [ 9:11] ACTTORW Activate to read/write
; [12:15] CASLAT CAS latency from read
; [16:19] REFREC Refresh recovery time
; [20] ---- Reserved (should be 0)
; [21:23] WRREC Last data to precharge
; [24] ---- Reserved (should be 0)
; [25:27] ACTTOACT Activate-to-activate
; [28] ---- Reserved (should be 0)
; [29:31] WRTORD Last write to read
;
; Configure for;
; PRETOACT = 011b 3 clocks
; ACTTOPRE = 0110b 6 clocks
; ACTTORW = 011b 3 clocks
; CASLAT = 0011b 2 clocks
; REFREC = 0010b 10 clocks
; WRREC = 011b 3 clocks
; ACTTOACT = 010b 2 clock
; WRTORD = 001b 1 clocks
;
WM32 0xE0002108 0x36332321 ;TIMING_CFG_1
; TIMING_CFG_2 (p9-13 [1])
; [ 0: 3] ---- Reserved
; [ 4: 7] CPO CAS-to-preamble override
; [ 8:11] ---- Reserved
; [12] ACSM Address and control shift mode
; [13:18] ---- Reserved
; [19:21] WR_DATA_DELAY Write command to write data
; [22:31] ---- Reserved
;
; U-Boot 1.3.1 has this Configured as;
; CPO = 0000b CASLAT + 1
; ACSM = 0b Default mode
; WR_DATA_DELAY = 010b 1/2 clock delay
;
WM32 0xE000210C 0x00000800 ;TIMING_CFG_2
; DDR Control Configuration (p9-14 [1])
; -------------------------------------
;
; Disable the controller during configuration.
;
; DDR_SDRAM_CFG
; [0] MEM_EN DDR interface enable
; [1] SREN Self-refresh enable
; [2] ECC_EN ECC enable
; [3] RD_EN Registered DIMM enable
; [ 4: 5] ---- Reserved
; [ 6: 7] SDRAM_TYPE Device type (10b DDR1, read-only)
; [ 8: 9] ---- Reserved
; [10] DYN_PWR Dynamic power management mode
; [11] ---- Reserved
; [12] 32_BE 32-bit bus enable
; [13] 8_BE 8-beat burst enable (DDR1 only)
; [14] NCAP Non-concurrent auto-precharge
; [15] ---- Reserved
; [16] 2T_EN Enable 2T timing
; [17:31] ---- Reserved
;
; Configure for;
; MEM_EN = 0b Disabled
; SREN = 1b Self-refresh enabled (during sleep)
; ECC_EN = 0b ECC disabled
; RD_EN = 0b Unbuffered DIMM
; SDRAM_TYPE = 10b DDR1 SDRAM
; DYN_PWR = 0b Dynamic power management disabled
; 32_BE = 0b 64-bit bus
; 8_BE = 0b 4-beat bursts used
; NCAP = 0b DRAMs support concurrent precharge
; 2T_EN = 0b 1T timing is used
;
WM32 0xE0002110 0x42000000 ;DDR_SDRAM_CFG
; DDR mode configuration (p9-15 [1])
; ----------------------
; DDR_SDRAM_MODE
; [ 0:15] ESDMODE Extended SDRAM mode
; [16:31] SDMODE SDRAM mode
;
; The mode settings are defined by the DDR memory manufacturer.
;
; The MPC8349E-MDS-PB DDR1 SODIMM markings are:
; - Micron MT8VDDT3264HDY-335F3 (can be found on Micron web site)
; 256MB, DDR, 333MHz, CL2.5, non-ECC
; - Micron's web site can be used to locate the product page for
; MT8VDDT3264HDY-335, and that page contains a link to
; the SPD EEPROM settings for the F3 version.
; - The modules have 8 pcs of MT46V16M16-6T 256Mb,
; 4M x 16-bit x 4 banks SDRAM.
; - This explains why the 256MB 64-bit module requires two
; chip-selects; one each for each block of four 16-bit chips.
;
; Notes from the Micron data sheet [3];
; - p1; the -6T part can operate at 133MHz and 167MHz
; - p2. 16-bit data
; 512 page size (1KB data) (9-bits column address)
; 32MB/1K = 32K (15-bits bank+row address)
; 2-bit bank, 13-bit row, 9-bit column addressing
;
; Mode Register (BA[1:0] = 00b) (p47 [3])
; MODE
; [ n: 7] OM Operating mode (two valid modes)
; [ 6: 4] CL CAL Latency
; [3] BT Burst type
; [ 2: 0] BL Burst length
;
; Extended mode 1 register (BA[1:0] = 01b) (p51 [3])
; EXTMODE
; [ n: 2] OM Operating mode (must be zero)
; [1] DS Drive strength
; [0] DLL DLL enable
;
; Reduced drive-strength only on x16 modules
;
; U-Boot 1.3.1 mode and extended mode settings:
;
; Configure the SDMODE register for;
; CL = 010b CL 2
; BT = 0b Sequential burst
; BL = 010b Burst length of 4
;
; SDMODE = 0000_0000_0010_0010b = 0022h
;
; DS = 0b Full-strength drive
; DLL = 0b DLL enabled
;
; EXTMODE = 0000_0000_0000_0000b = 0000h
;
WM32 0xE0002118 0x00000022 ;DDR_SDRAM_MODE
; DDR Interval Configuration (p9-16, p9-44 [1])
; --------------------------
; DDR_SDRAM_INTERVAL
; [ 0: 1] ----
; [ 2:15] REFINT Refresh interval
; [16:17] ----
; [18:31] BSTOPRE Precharge interval
;
; Refresh interval:
; - DDR device requirement: tREFI = 7.81us (p22, p29 note 24 [3])
; - The DDR clocks operate at 132MHz (264MHz data rate)
; - Number of DDR clocks per tREFI:
; 132MHz x 7.81us = 1030 clocks (406h)
; - This matches the U-Boot setting
; - Technically the clock count should have the number of
; clocks for the longest possible transaction subtracted
; from this value (p9-56 [1]).
;
; Precharge interval
; - U-Boot has it as 100h, so 1.94us (about tREFI/4).
; - p9-44 discusses open-page mode, and the MPC8349EA manual
; indicates that BSTOPRE can be set to any value.
;
WM32 0xE0002124 0x04060100 ;DDR_SDRAM_INTERVAL
; Delay before enabling the DDR controller
; (p9-49 indicates at least a 200us delay is required)
DELAY 300
; DDR Control Configuration (p9-14 [1])
; -------------------------------------
;
; This write enables the controller, so should occur after
; the other DDR registers are configured.
;
; DDR_SDRAM_CFG
; [0] MEM_EN DDR interface enable
; [1] SREN Self-refresh enable
; [2] ECC_EN ECC enable
; [3] RD_EN Registered DIMM enable
; [ 4: 5] ---- Reserved
; [ 6: 7] SDRAM_TYPE Device type (10b DDR1, read-only)
; [ 8: 9] ---- Reserved
; [10] DYN_PWR Dynamic power management mode
; [11] ---- Reserved
; [12] 32_BE 32-bit bus enable
; [13] 8_BE 8-beat burst enable (DDR1 only)
; [14] NCAP Non-concurrent auto-precharge
; [15] ---- Reserved
; [16] 2T_EN Enable 2T timing
; [17:31] ---- Reserved
;
; Configure for;
; MEM_EN = 1b Enabled
; SREN = 1b Self-refresh enabled (during sleep)
; ECC_EN = 0b ECC disabled
; RD_EN = 0b Unbuffered DIMM
; SDRAM_TYPE = 10b DDR1 SDRAM
; DYN_PWR = 0b Dynamic power management disabled
; 32_BE = 0b 64-bit bus
; 8_BE = 0b 4-beat bursts used
; NCAP = 0b DRAMs support concurrent precharge
; 2T_EN = 0b 1T timing is used
;
WM32 0xE0002110 0xC2000000 ;DDR_SDRAM_CFG
; Local-bus Controller
; --------------------
;
; Setup chip selects
;
; Base Register (p10-11)
; BRn
; [ 0:16] BA Base address (17-bits)
; [17:18] ---- Reserved
; [19:20] PS Port size
; [21:22] DECC Data ECC method
; [23] WP Write protect
; [24:26] MSEL Machine select (GPCM, SDRAM, UPM)
; [27:30] ---- Reserved
; [31] V Valid bit (BRn and ORn are valid)
;
; Options Register (p10-12)
; ORn
; [ 0:16] AM Address mask (defines the region size)
; [17:18] ---- Reserved
; [19] BCTLD Buffer control disable (LBCTL)
; [20] CSNT Chip-select negation time
; [21:22] ACS Address to chip-select setup
; [23] XACS Extra address to chip-select setup
; [24:27] SCY Cycle length in bus clocks
; [28] SETA External address termination
; [29] TRLX Timing relaxed
; [30] EHTR Extended hold time on read accesses
; [31] EAD External address latch delay
;
; The options register (ORn) should be set first, and
; then the base register (BRn), with the valid bit set.
;
; The reset state for 16-bit Flash boot is:
; BR0 = 0000_1001h
; BA = 0h Flash is at address 0h
; PS = 10b 16-bits
; DECC = 00b Data error checking disabled
; WP = 0b R/W allowed
; MSEL = 000b GPCM
; V = 1b Valid (enabled)
;
; OR0 = 0000_0FF7h
; AM = 0b 4GB decode
; BCTLD = 0b LBCTL asserts
; CSNT = 1b LCS#0 and LWE# assert 1/4 clock earlier
; ACS = 11b LCS#0 asserts half a clock after address
; XACS = 1b Address to chip select extended
; SCY = 1111b 15 clocks of wait-states
; SETA = 0b Internal termination
; TRLX = 1b Relaxing timing
; EHTR = 1b Extended hold on read accesses (8 clocks)
; EAD = 1b LALE asserted for 4 clocks
;
; The RCWs and local bus LAW reset settings generate an 8MB
; window located at address 0.
;
; The settings for the 8MB Micron Flash located at
; FE00_0000h (the address window setup above) just modify
; the base address, and address mask fields to put the
; 8MB flash starting at 32MB from the end of memory
; (since the MPC8349EA-MDS-PB contains a 32MB Flash).
; The access timing settings remain the same.
;
WM32 0xE0005004 0xFF800FF7 ;OR0 : Flash 8MB
WM32 0xE0005000 0xFE001001 ;BR0 : Flash
WM32 0xE000500C 0xFFFFE8F0 ;OR1 : BCSR 32kB
WM32 0xE0005008 0xE2400801 ;BR1 : BCSR
; Enable flash programming
; ------------------------
;
; Write to the BCSR to deassert write-protect (WP# = 1), and
; write to the Micron Q-Flash to clear the block lock bits
; (p15 [4])
;
WM8 0xE2400001 0x0C ;BCSR
WM16 0xFE000000 0x0060 ;Flash
WM16 0xFE000000 0x00D0
DELAY 1000
WM16 0xFE000000 0xFFFF
; =================================================================
[TARGET]
CPUTYPE 8349 ;the CPU type
JTAGCLOCK 0 ;use 16 MHz JTAG clock
POWERUP 2000 ;start delay after power-up detected in ms
WAKEUP 500 ;give reset time to complete
STARTUP RESET ;halt immediately at the boot vector
; Reset Configuration Words (p4-12 [1])
; -------------------------
;
; The BDI2000 RCW command can be used to over-ride the RCWs.
; This is useful when the RCWs will be fetched from Flash,
; but the Flash is empty.
;
; The configuration of the RCWs can be done using the clock
; and reset tool (GUI) available on Freescale's web site.
;
; Reset Configuration Words Low Register
; ---------------------------------------
; RCWLR (p4-13 [1])
; [0] LBIUCM Local bus interface unit clock mode
; [1] DDRCM DDR clock mode
; [ 2: 3] ---- Reserved
; [ 4: 7] SPMF System PLL multiplication factor
; [8] ---- Reserved
; [ 9:15] COREPLL Core PLL configuration
; [16:31] ---- Reserved
;
; Configure for 66MHz external clock;
; LBIUCM = 0b 1:1 Mode (lbc_clk = 264MHz)
; DDRCM = 0b 1:1 Mode (ddr_clk = 264MHz)
; SPMF = 0100b x4 (csb_clk = 264MHz = 66MHz x 4)
; COREPLL = 0000100b x2 (core_clk = 528MHz, VCO 1056MHz)
;
; Reset Configuration Words High Register
; ---------------------------------------
; RCWL (p4-13 [1])
; [0] PCIHOST PCI host/agent mode
; [1] PCI64 PCI 64-bit mode
; [2] PCI1ARB PCI1 internal arbiter mode
; [3] PCI2ARB PCI2 internal arbiter mode
; [4] COREDIS Core disable mode
; [5] BMS Boot memory space
; [ 6: 7] BOOTSEQ Boot sequencer configuration
; [8] SWEN Software watchdog enable
; [ 9:11] ROMLOC Boot ROM interface location
; [12:15] ---- Reserved (should be 0)
; [16:17] TSEC1M TSEC1 mode
; [18:19] TSEC2M TSEC2 mode
; [20-27] ---- Reserved (should be 0)
; [28] TLE True little-endian
; [29] LALE Local bus LALE timing
; [30] LDP LDP pin mux state after reset
; [31] ---- Reserved (should be 0)
;
; Configure for host-mode, local-bus Flash low-memory boot;
; PCIHOST = 1b Host-mode
; PCI64 = 0b 32-bit (PCI1 and PCI2 enabled)
; PCI1ARB = 1b PCI1 arbiter enabled
; PCI2ARB = 1b PCI2 arbiter enabled
; COREDIS = 0b Core enabled
; BMS = 0b Low-memory boot
; BOOTSEQ = 00b Boot sequencer disabled
; SWEN = 0b Watchdog disabled
; ROMLOC = 110b 16-bit local bus GPCM
; TSEC1M = 10b GMII mode
; TSEC2M = 10b GMII mode
; TLE = 0b Big-endian mode
; LALE = 0b Normal timing
; LDP = 0b Local data parity
;
; Format: RCW RCWH RCWL
;RCW 0xB060A000 0x04040000
BOOTADDR 0x00000100 ;boot address used for start-up break
BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint
;MMU XLAT 0xc0000000 ;enable address translation
;SIO 8023 115200
; =================================================================
[HOST]
IP 192.168.17.61
;FILE c:\test\test.elf
;FORMAT ELF
;FILE c:\temp\dump512k.bin
FORMAT BIN 0x10000
LOAD MANUAL ;load code MANUAL or AUTO after reset
PROMPT 8349>
; =================================================================
[FLASH]
CHIPTYPE STRATAX16 ;Flash type: Micron Q-Flash MT28F640J3
CHIPSIZE 0x800000 ;The size of one flash chip in bytes
BUSWIDTH 16 ;The width of the flash memory bus in bits
; (8 | 16 | 32 | 64)
WORKSPACE 0x1000 ;workspace in DDR RAM
FILE u-boot-1.3.1.bin
FORMAT BIN 0xfe000000
ERASE 0xfe000000 ;erase sector 0 (128kB sectors)
ERASE 0xfe020000 ;erase sector 1
; =================================================================
[REGS]
FILE $reg8349e.def
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