I don't know the background why this lock added. So if I miss something,
please let me know. Or I'll push this before merge window close().
========>
I don't see any reason why we have to lock cache line here. Maybe some
targets require this locking, but that's completely target specific re-
quirement and we should not have such things in global start codes.
Signed-off-by: Shinya Kuribayashi <[EMAIL PROTECTED]>
---
cpu/mips/cache.S | 26 --------------------------
cpu/mips/start.S | 5 -----
2 files changed, 0 insertions(+), 31 deletions(-)
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 443240e..9d793bf 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -237,29 +237,3 @@ dcache_disable:
j ra
.end dcache_disable
-
-/*******************************************************************************
-*
-* mips_cache_lock - lock RAM area pointed to by a0 in cache.
-*
-* RETURNS: N/A
-*
-*/
-#if defined(CONFIG_PURPLE)
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
-#else
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
-#endif
- .globl mips_cache_lock
- .ent mips_cache_lock
-mips_cache_lock:
- li a1, K0BASE - CACHE_LOCK_SIZE
- addu a0, a1
- li a2, CACHE_LOCK_SIZE
- li a3, CFG_CACHELINE_SIZE
- move a1, a2
- icacheop(a0,a1,a2,a3,0x1d)
-
- j ra
-
- .end mips_cache_lock
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index c92b162..fd44da0 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -267,11 +267,6 @@ reset:
/* Set up temporary stack.
*/
- li a0, CFG_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
- nop
-
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
la sp, 0(t0)
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