On Mon, Mar 17, 2008 at 4:04 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote: > In message <[EMAIL PROTECTED]> you wrote: > > I don't know the background why this lock added. So if I miss something, > > please let me know. Or I'll push this before merge window close(). > ... > > /* Set up temporary stack. > > */ > > - li a0, CFG_INIT_SP_OFFSET > > - la t9, mips_cache_lock > > - jalr t9 > > - nop > > - > > Isn't the lock necessary to use the cache as memory for stack and > initial data?
This code has some problems: Cache locking is not consistent across MIPS implementations. Some implementations do not support locking at all. The style of locking varies - some support per line locking, others per way, etc, etc. Some parts use bits in status registers instead of the cache ops. IIRC, some MIPS cache implementations require valid zeroed RAM to init cache parity correctly. The cache never gets unlocked, so the code relies on whatever gets loaded after u-boot to reinitialize the cache and clear the locks. -- Hardware, n.: The parts of a computer system that can be kicked. ------------------------------------------------------------------------- This SF.net email is sponsored by: Microsoft Defy all challenges. Microsoft(R) Visual Studio 2008. http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ _______________________________________________ U-Boot-Users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/u-boot-users
