Hello, BTW, when I said "recommended by AMCC" in the patch description I referred to the following information forwarded to me by Wolfgang Denk on Tue Mar 18 2008:
--- Dear Yuri, here is some additional (and hopefully helpful) information from AMCC regarding the observed hangs on the katmai board: > If possible, can you please check if you still see the lock up when > you program MQ as follows: > set value in HB and if you are using LL also as follows: > MQ0_CF1H = 0x80001C80 > MQ0_CF1L = 0x80001C80 > Additionally, make sure that your PLB settings are: > PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) > PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) > Please let me know if this fixes the issue. > I also would like to know how you are programming your DMA and how > is the traffic is pipelined. > Regards, > Olga Buchonina > AMCC PowerPC Applications Engineering Best regards, Wolfgang Denk --- On Tuesday, September 23, 2008 you wrote: > Hi Yuri, > On Tuesday 23 September 2008, Yuri Tikhonov wrote: >> Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC >> values. This fixes the occasional 440SPe hard locking issues when the >> 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID >> driver). >> >> Previously the appropriate initialization had been made in Linux, by the >> ppc440spe ADMA driver, which is wrong because modifying the MQ >> configuration registers after normal operation has begun is not supported >> and could have unpredictable results. > AMCC just recently updated the 440SP(e) MQ initialization with this patch: > commit 079589bcfb24ba11068460276a3cc9549ab5346f > Author: Prodyut Hazarika <[EMAIL PROTECTED]> > Date: Wed Aug 20 09:38:51 2008 -0700 > ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe, > PPC405EX and PPC460EX/GT/SX > - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX > processors > - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared > across processors (405 and 440/460) > - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX > processors > - Add register bit definitions for Memory Queue Configuration registers > Signed-off-by: Prodyut Hazarika <[EMAIL PROTECTED]> > Signed-off-by: Stefan Roese <[EMAIL PROTECTED]> > I have a bad feeling changing this "optimized" settings without AMCC's > specific ACK. > Prodyut, are you ok with Yuri's change? > Thanks. > Best regards, > Stefan > ===================================================================== > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] > ===================================================================== Regards, Yuri -- Yuri Tikhonov, Senior Software Engineer Emcraft Systems, www.emcraft.com _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot