Hi Yuri/Stefan, I remember duriing my testing that the default Read passing limit (RPML) and MCIF limit (WRCL) was 1. So there was no need to set these registers again to the same values. Thanks, Prodyut : Tue 9/23/2008 2:43 AM To: Yuri Tikhonov Cc: u-boot@lists.denx.de; Prodyut Hazarika; Olga Buchonina Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
On Tuesday 23 September 2008, Yuri Tikhonov wrote: > BTW, when I said "recommended by AMCC" in the patch description I > referred to the following information forwarded to me by Wolfgang > Denk on Tue Mar 18 2008: > > --- > Dear Yuri, > > here is some additional (and hopefully helpful) information from AMCC > > regarding the observed hangs on the katmai board: > > If possible, can you please check if you still see the lock up when > > you program MQ as follows: > > set value in HB and if you are using LL also as follows: > > MQ0_CF1H = 0x80001C80 > > MQ0_CF1L = 0x80001C80 > > Additionally, make sure that your PLB settings are: > > PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) > > PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) > > Please let me know if this fixes the issue. > > I also would like to know how you are programming your DMA and how > > is the traffic is pipelined. > > Regards, > > Olga Buchonina > > AMCC PowerPC Applications Engineering Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] =====================================================================
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