Hi Amar, ..snip.. >> I didn't understand this function(exynos5_mmc_set_clk_div?). >> What purpose? I think good that proper to use the "div" as argument. >> void exynos5_mmc_set_clk(int dev_id, unsigned int div). > > > For fixing dwmmc driver, I referred to working code from > "chromiumos/src/third_party/u-boot". > In chromium uboot, during mhci init, the function "clock_set_mshci()" is > called which is in "arch/arm/cpu/armv7/exynos5/clock.c" > > Our function "*exynos5_mmc_set_clk_div()"* is same as "*clock_set_mshci()".* > > Now coming to 'div' as argument .... we have the below scenarios / questions > 1-> What is the value of 'div' to be passed from calling function ? It will be the pre_ratio's value for FSYSx register.
> 2-> The value of 'div' needs to be computed in calling function. It will be computed before called this function. For example, in dw_mmc.c or exynos_dw_mc.c > 3-> As per my understanding, 'div' value depends on values of MPLL clock > and FSYS1/2. Right..but it will be changed the source clock. MMC/SD can use the every source clock. > 4-> *Question:* Is it OK to put the piece of code which accesses MPLL, > FSYS1, FSYS2 in drivers/mmc/exynos_dw_mmc.c. ? Sure..we can use the get_mmc_clk/set_mmc_clk. then we can get source clock value. and compute the div value for request clock. > 5-> If we compute 'div' value in "drivers/mmc/exynos_dw_mmc.c", then > there will be duplication of code (Read of FSYS1/2). What code is duplication? Could you explain to me more? Only need to compute the div value in exynos_dw_mmc.c. why need to compute into here? Best Regards, Jaehoon Chung > > Please comment on the above. > >> + >> /* get_lcd_clk: return lcd clock frequency */ >> static unsigned long exynos4_get_lcd_clk(void) >> { >> diff --git a/arch/arm/include/asm/arch-exynos/clk.h > b/arch/arm/include/asm/arch-exynos/clk.h >> index 1935b0b..2fd7c3e 100644 >> --- a/arch/arm/include/asm/arch-exynos/clk.h >> +++ b/arch/arm/include/asm/arch-exynos/clk.h >> @@ -29,6 +29,9 @@ >> #define VPLL 4 >> #define BPLL 5 >> >> +#define FSYS1_MMC0_DIV_MASK 0xff0f >> +#define FSYS1_MMC0_DIV_VAL 0x0701 >> + >> unsigned long get_pll_clk(int pllreg); >> unsigned long get_arm_clk(void); >> unsigned long get_i2c_clk(void); >> @@ -36,6 +39,7 @@ unsigned long get_pwm_clk(void); >> unsigned long get_uart_clk(int dev_index); >> unsigned long get_mmc_clk(int dev_index); >> void set_mmc_clk(int dev_index, unsigned int div); >> +int exynos5_mmc_set_clk_div(int dev_index); >> unsigned long get_lcd_clk(void); >> void set_lcd_clk(void); >> void set_mipi_clk(void); >> > > _______________________________________________ >> U-Boot mailing list >> U-Boot@lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot >> > > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot