On 21/03/13 21:13, Akshay Saraswat wrote:
> We intended to clear the bits of CLK_SRC_TOP2 register, instead we were
> writing on the reserved bits of src_core1 register. Since the default
> value of clk_src_top2 register were itself zero, this typo was not
> creating any big issue. But it is better to fix this error for better
> readability of the code.
>
> Signed-off-by: Hatim Ali <hatim...@samsung.com>
> Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
> ---
> board/samsung/smdk5250/clock_init.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/board/samsung/smdk5250/clock_init.c
> b/board/samsung/smdk5250/clock_init.c
> index c009ae5..0ee65ae 100644
> --- a/board/samsung/smdk5250/clock_init.c
> +++ b/board/samsung/smdk5250/clock_init.c
> @@ -434,10 +434,10 @@ void system_clock_init()
> val = readl(&clk->mux_stat_core1);
> } while ((val | MUX_MPLL_SEL_MASK) != val);
>
> - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
> - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
> + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
> tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
> | MUX_GPLL_SEL_MASK;
> do {
>
applied to u-boot-samsung.
Thanks,
Minkyu Kang
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