On Wed, Jun 12, 2013 at 4:40 PM, Armando Visconti <armando.visco...@st.com> wrote: > On 06/10/2013 06:01 PM, Jagan Teki wrote: >> >> Hi, >> >> Please use the commit header as below: just to sync with remaining >> drivers in tree. >> >> spi: arm-pl022: Add support for ARM PL022 spi controller >> > > OK, > I already did it for v5. > I'll keep it for v6 as well... > > >> On Fri, Jun 7, 2013 at 1:14 PM, Armando Visconti >> <armando.visco...@st.com> wrote: >>> >>> This patch adds the support for the ARM PL022 SPI controller for the >>> standard >>> variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX >>> FIFO. >>> >>> Signed-off-by: Armando Visconti <armando.visco...@st.com> >>> Signed-off-by: Vipin Kumar <vipin.ku...@st.com> >>> Acked-by: Stefan Roese <s...@denx.de> >>> --- >>> v3->v4 >>> Just removed all warnings when running checkpatch. >>> Didn't find Jagan's feedback... So, pls, let me know if we >>> need to change anything else... >>> >>> Armando >>> >>> drivers/spi/Makefile | 1 + >>> drivers/spi/pl022_spi.c | 310 >>> ++++++++++++++++++++++++++++++++++++++++++++++++ >>> 2 files changed, 311 insertions(+) >>> create mode 100644 drivers/spi/pl022_spi.c >>> >>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile >>> index d08609e..b6443b1 100644 >>> --- a/drivers/spi/Makefile >>> +++ b/drivers/spi/Makefile >>> @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o >>> COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o >>> COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o >>> COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o >>> +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o >>> COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o >>> COBJS-$(CONFIG_SH_SPI) += sh_spi.o >>> COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o >>> diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c >>> new file mode 100644 >>> index 0000000..8a8b9ab >>> --- /dev/null >>> +++ b/drivers/spi/pl022_spi.c >>> @@ -0,0 +1,310 @@ >>> +/* >>> + * (C) Copyright 2012 >>> + * Armando Visconti, ST Microelectronics, armando.visco...@st.com. >>> + * >>> + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c >>> + * by Atmel Corporation. >>> + * >>> + * This program is free software; you can redistribute it and/or >>> + * modify it under the terms of the GNU General Public License as >>> + * published by the Free Software Foundation; either version 2 of >>> + * the License, or (at your option) any later version. >>> + * >>> + * This program is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + * >>> + * You should have received a copy of the GNU General Public License >>> + * along with this program; if not, write to the Free Software >>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, >>> + * MA 02111-1307 USA >>> + */ >>> + >>> +#include <common.h> >>> +#include <malloc.h> >>> +#include <spi.h> >>> +#include <asm/io.h> >>> +#include <asm/arch/hardware.h> >>> + >>> +/* SSP registers mapping */ >>> +struct pl022 { >>> + u32 ssp_cr0; /* 0x000 */ >>> + u32 ssp_cr1; /* 0x004 */ >>> + u32 ssp_dr; /* 0x008 */ >>> + u32 ssp_sr; /* 0x00c */ >>> + u32 ssp_cpsr; /* 0x010 */ >>> + u32 ssp_imsc; /* 0x014 */ >>> + u32 ssp_ris; /* 0x018 */ >>> + u32 ssp_mis; /* 0x01c */ >>> + u32 ssp_icr; /* 0x020 */ >>> + u32 ssp_dmacr; /* 0x024 */ >>> + u8 reserved_1[0x080 - 0x028]; >>> + u32 ssp_itcr; /* 0x080 */ >>> + u32 ssp_itip; /* 0x084 */ >>> + u32 ssp_itop; /* 0x088 */ >>> + u32 ssp_tdr; /* 0x08c */ >>> + u8 reserved_2[0xFE0 - 0x090]; >>> + u32 ssp_pid0; /* 0xfe0 */ >>> + u32 ssp_pid1; /* 0xfe4 */ >>> + u32 ssp_pid2; /* 0xfe8 */ >>> + u32 ssp_pid3; /* 0xfec */ >>> + u32 ssp_cid0; /* 0xff0 */ >>> + u32 ssp_cid1; /* 0xff4 */ >>> + u32 ssp_cid2; /* 0xff8 */ >>> + u32 ssp_cid3; /* 0xffc */ >>> +}; >>> + >>> +/* SSP Control Register 0 - SSP_CR0 */ >>> +#define SSP_CR0_SPO (0x1 << 6) >>> +#define SSP_CR0_SPH (0x1 << 7) >>> +#define SSP_CR0_8BIT_MODE (0x07) >>> +#define SSP_SCR_MAX (0xFF) >>> +#define SSP_SCR_SHFT 8 >>> + >>> +/* SSP Control Register 0 - SSP_CR1 */ >>> +#define SSP_CR1_MASK_SSE (0x1 << 1) >>> + >>> +#define SSP_CPSR_MAX (0xFE) >>> + >>> +/* SSP Status Register - SSP_SR */ >>> +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty >>> */ >>> +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not >>> full */ >>> +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not >>> empty */ >>> +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full >>> */ >>> +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ >>> + >>> +struct pl022_spi_slave { >>> + struct spi_slave slave; >>> + void *regs; >>> + unsigned int freq; >>> +}; >>> + >>> +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave >>> *slave) >>> +{ >>> + return container_of(slave, struct pl022_spi_slave, slave); >>> +} >>> + >> >> ------ TAG+ >>> >>> +/* >>> + * Following three functions should be provided by the >>> + * board support package. >>> + */ >>> +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) >>> +{ >>> + return 1; >>> +} >>> + >>> +void __weak spi_cs_activate(struct spi_slave *slave) >>> +{ >>> + /* do nothing */ >>> +} >>> + >>> +void __weak spi_cs_deactivate(struct spi_slave *slave) >>> +{ >>> + /* do nothing */ >>> +} >>> + >>> +void spi_init(void) >>> +{ >>> + /* do nothing */ >>> +} >> >> -------------------- TAG- >> >> Any specific reason for defining theese on to board? >> Would it be possible to do the same here, as these are spi specific. >> >> I am trying to collaborate the spi code to generic, so-that it has >> some identity as other >> driver did. > > > The pl022 SPI controller, differently from other SPI controller, does > not provide a chip select pin. > Therefore the CS must handled in a soc-specific way. > What the driver has to do is to provide dummy functions that MUST be > overwritten by soc specific ones. > > If you see the pl022 linux driver does the same. > > > >> >>> + >>> +/* >>> + * ARM PL022 exists in different 'flavors'. >>> + * This drivers currently support the standard variant (0x00041022), >>> that has a >>> + * 16bit wide and 8 locations deep TX/RX FIFO. >>> + */ >>> +static int pl022_is_supported(struct pl022_spi_slave *ps) >>> +{ >>> + struct pl022 *pl022 = (struct pl022 *)ps->regs; >>> + >>> + /* PL022 version is 0x00041022 */ >>> + if ((readl(&pl022->ssp_pid0) == 0x22) && >>> + (readl(&pl022->ssp_pid1) == 0x10) && >>> + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && >>> + (readl(&pl022->ssp_pid3) == 0x00)) >> >> >> Tab space is required, for this if statement i guess, please check. >> > > If I do then checkpatch reports a warning, saying that I need to keep > all lines of a 'if' statement aligned properly... > > So, I guess that this way is more proper.
Agree, but it should be easy to interpret where should the if block end and where should the code block starts. I always use tab space like +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} If you see return 1 is code block, so prior to this if ends. -- Thanks, Jagan. > > > >>> + return 1; >>> + >>> + return 0; >>> +} >>> + >>> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, >>> + unsigned int max_hz, unsigned int mode) >>> +{ >>> + struct pl022_spi_slave *ps; >>> + struct pl022 *pl022; >>> + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; >>> + >>> + if (!spi_cs_is_valid(bus, cs)) >>> + return NULL; >>> + >> >> >> ----- TAG+ >>> >>> + ps = malloc(sizeof(*ps)); >>> + if (!ps) >>> + return NULL; >>> + >>> + ps->slave.bus = bus; >>> + ps->slave.cs = cs; >> >> ----- TAG- >> >> Code from TAG+ to TAG-, please use spi_alloc_slave() >> refer any ddriver in rivers/spi/* >> > > ok, I'll do it! > > Pls let me know if we are now fine... > > Thx, > Arm > > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot