[U-Boot] [PATCH v2 3/4] LaCie/common: Fix cloudbox ethernet leds

[Frédéric Leroy]

The cloudbox device have a different ethernet phy setup than other ns2
devices. We get initialization value from the GPL LaCie source

Signed-off-by: Frédéric Leroy <fr...@starox.org>
---
 board/LaCie/common/common.c | 13 ++++++++++---
 include/configs/lacie_kw.h  |  5 +++++
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c
index a62bf9f..85480e7 100644
--- a/board/LaCie/common/common.c
+++ b/board/LaCie/common/common.c
@@ -21,6 +21,12 @@
 #define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
 #define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
 
+#if !defined(MII_MARVELL_LED_REG)
+# define MII_MARVELL_LED_REG 16
+# define MII_MARVELL_LED_MASK 0xf0
+# define MII_MARVELL_LED_VALUE 0x0f
+#endif
+
 void mv_phy_88e1116_init(const char *name, u16 phyaddr)
 {
        u16 reg;
@@ -53,9 +59,10 @@ void mv_phy_88e1318_init(const char *name, u16 phyaddr)
         * Set control mode 4 for LED[0].
         */
        miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
-       miiphy_read(name, phyaddr, 16, &reg);
-       reg |= 0xf;
-       miiphy_write(name, phyaddr, 16, reg);
+       miiphy_read(name, phyaddr, MII_MARVELL_LED_REG, &reg);
+       reg &= MII_MARVELL_LED_MASK;
+       reg |= MII_MARVELL_LED_VALUE;
+       miiphy_write(name, phyaddr, MII_MARVELL_LED_REG, reg);
 
        /*
         * Enable RGMII delay on Tx and Rx for CPU port
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index fe27bbe..02e0882 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -138,6 +138,11 @@
 #ifdef CONFIG_CMD_NET
 #define CONFIG_MVGBE_PORTS             {1, 0} /* enable port 0 only */
 #define CONFIG_NETCONSOLE
+#if defined(CONFIG_CLOUDBOX)
+# define MII_MARVELL_LED_REG 17
+# define MII_MARVELL_LED_MASK 0xffc0
+# define MII_MARVELL_LED_VALUE 0x15
+#endif
 #endif
 
 /*
-- 
1.8.1.2

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