From: Christoph G. Baumann <c.baum...@ppc-ag.de>
The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn
DRAM controller registers so the DRAM module will be correctly
recognised.
Signed-off-by: Christoph G. Baumann <c.baum...@ppc-ag.de>
Cc: Marek Vasut <ma...@denx.de>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@freescale.com>
---
board/ppcag/bg0900/spl_boot.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
index 2616e1f..a04c955 100644
--- a/board/ppcag/bg0900/spl_boot.c
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -118,6 +118,19 @@ const iomux_cfg_t iomux_setup[] = {
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
+ /*
+ * DDR Controller Registers
+ * Manufacturer: Winbond
+ * Device Part Number: W972GG6JB-25I
+ * Clock Freq.: 200MHz
+ * Density: 2Gb
+ * Chip Selects: 1
+ * Number of Banks: 8
+ * Row address: 14
+ * Column address: 10
+ */
+
+ dram_vals[0x74 / 4] = 0x0102010A;
dram_vals[0x98 / 4] = 0x04005003;
dram_vals[0x9c / 4] = 0x090000c8;
--
1.8.4.rc3
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