Hi Eric,
> Thanks Marek,
>
> On 11/11/2013 09:22 AM, Marek Vasut wrote:
> > Enable PCI express on MX6 Sabrelite.
> >
> > Signed-off-by: Marek Vasut <ma...@denx.de>
> > Cc: Albert Aribaud <albert.u.b...@aribaud.net>
> > Cc: Eric Nelson <eric.nel...@boundarydevices.com>
> > Cc: Fabio Estevam <fabio.este...@freescale.com>
> > Cc: Stefano Babic <sba...@denx.de>
> > ---
> >
> > board/boundary/nitrogen6x/nitrogen6x.c | 7 ++++++-
> > include/configs/nitrogen6x.h | 11 +++++++++++
> > 2 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/boundary/nitrogen6x/nitrogen6x.c
> > b/board/boundary/nitrogen6x/nitrogen6x.c index 1712908..46be51e 100644
> > --- a/board/boundary/nitrogen6x/nitrogen6x.c
> > +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> > @@ -369,7 +369,12 @@ int board_eth_init(bd_t *bis)
> >
> > free(bus);
> >
> > }
> >
> > #endif
> >
> > - return 0;
> > +
>
> I think this bit needs a different configuration option
> and should be disabled by default.
This activates all PCI/PCI-express ethernet cards, that's why CONFIG_PCI. I
suppose testing CONFIG_CMD_NET would be a good idea here as well.
> > +#ifdef CONFIG_PCI
> > + ret = pci_eth_init(bis);
> > +#endif
> > +
>
> It seems to lock up the system if you don't have the proper
> device connected.
I am attaching you a patch, can you please try with the attached patch ? It
should fix your enumeration issue.
btw. I noticed there's no PCIe reset connected on the sabrelite, that's a bit
bad, we found out the PCIe reset should be connected, otherwise the PCIe will
misbehave upon init sometimes.
> Without this bit, I was able to confirm proper enumeration
> of a PCIe bus with a USB 3.0 controller:
>
> 00:01.0 - 16c3:abcd - Bridge device
> 01:00.0 - 1b21:0612 - Mass storage controller
>
> Unfortunately, in a quick test, the image fails to boot
> without a PCIe device connected, or oddly, with a different
> PCIe ethernet controller connected.
>
> I think it's handy to have the placeholder here, but
> I think you're the only person on the planet with the
> right set of components to make it work at the moment.
I'd usually be proud by hearing that, but ... I can't say I'm too happy about
this ;-)
Best regards,
Marek Vasut
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 12e3546..3f55810 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -35,6 +35,8 @@
#define PL_OFFSET 0x700
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -216,8 +218,9 @@ static int imx6_pcie_link_up(void)
int rx_valid, temp;
/* link is debug bit 36, debug register 1 starts at bit 32 */
- rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
- if (rc)
+ rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
+ if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+ !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
return -EAGAIN;
/*
@@ -447,7 +450,7 @@ static int imx6_pcie_init_phy(void)
(127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
(127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
&iomuxc_regs->gpr[8]);
-
+
return 0;
}
@@ -467,7 +470,7 @@ static int imx6_pcie_deassert_core_reset(void)
* Wait for the clock to settle a bit, when the clock are sourced
* from the CPU, we need about 30mS to settle.
*/
- udelay(30000);
+ mdelay(30);
return 0;
}
@@ -499,14 +502,14 @@ static int imx_pcie_link_up(void)
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
while (!imx6_pcie_link_up()) {
- udelay(1000);
+ udelay(10);
count++;
if (count >= 2000) {
debug("phy link never came up\n");
debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
- break;
+ return -EINVAL;
}
}
@@ -518,6 +521,7 @@ void imx_pcie_init(void)
/* Static instance of the controller. */
static struct pci_controller pcc;
struct pci_controller *hose = &pcc;
+ int ret;
memset(&pcc, 0, sizeof(pcc));
@@ -547,10 +551,12 @@ void imx_pcie_init(void)
imx_pcie_write_config);
/* Start the controller. */
- imx_pcie_link_up();
+ ret = imx_pcie_link_up();
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
+ if (!ret) {
+ pci_register_hose(hose);
+ hose->last_busno = pci_hose_scan(hose);
+ }
}
/* Probe function. */
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