> -----Original Message-----
> From: Dirk Behme [mailto:dirk.be...@googlemail.com]
> Sent: Wednesday, May 06, 2009 8:25 PM
> To: Matthias Ludwig; Pillai, Manikandan
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] OMAP3EVM: net_chip uses CS5 not CS6
>
> Matthias Ludwig wrote:
> > Signed-off-by: Matthias Ludwig <mlud...@ultratronik.de>
>
> Matthias: Thanks for fixing this!
[Pillai, Manikandan] not sure why this change in the Chip select
>
> Mani: Can we get your ack as EVM maintainer?
>
> Many thanks and best regards
>
> Dirk
>
> > ---
> > board/omap3/evm/evm.c | 16 ++++++++--------
> > include/asm-arm/arch-omap3/cpu.h | 5 +++--
> > 2 files changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
> > index c008c2e..5fd5efa 100644
> > --- a/board/omap3/evm/evm.c
> > +++ b/board/omap3/evm/evm.c
> > @@ -92,17 +92,17 @@ void set_muxconf_regs(void)
> > static void setup_net_chip(void)
> > {
> > gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
> > - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
> > + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
> > ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
> >
> > /* Configure GPMC registers */
> > - writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
> > - writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
> > - writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
> > - writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
> > - writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
> > - writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
> > - writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
> > + writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
> > + writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
> > + writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
> > + writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
> > + writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
> > + writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
> > + writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
> >
> > /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> > writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> > diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-
> omap3/cpu.h
> > index c544e0c..a4ce45a 100644
> > --- a/include/asm-arm/arch-omap3/cpu.h
> > +++ b/include/asm-arm/arch-omap3/cpu.h
> > @@ -84,9 +84,10 @@ typedef struct ctrl_id {
> > /* GPMC CS3/cs4/cs6 not avaliable */
> > #define GPMC_BASE (OMAP34XX_GPMC_BASE)
> > #define GPMC_CONFIG_CS0 0x60
> > -#define GPMC_CONFIG_CS6 0x150
> > +#define GPMC_CONFIG_CS5 0x150
> > +
> > #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
> > -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
> > +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
> > #define GPMC_CONFIG_WP 0x10
> >
> > #define GPMC_CONFIG_WIDTH 0x30
>
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