O accessors instead of pointer accesses

Wolfgang Denk Sat, 09 May 2009 13:00:03 -0700

Signed-off-by: Wolfgang Denk <w...@denx.de>
Cc: John Rigby <jcri...@gmail.com>
---
 drivers/net/mpc512x_fec.c |  113 +++++++++++++++++++++++++-------------------
 1 files changed, 64 insertions(+), 49 deletions(-)


diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 10a78ab..fe28bdf 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -11,6 +11,7 @@
 #include <net.h>
 #include <netdev.h>
 #include <miiphy.h>
+#include <asm/io.h>
 #include "mpc512x_fec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -65,7 +66,8 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
         * Receive BDs init
         */
        for (ix = 0; ix < FEC_RBD_NUM; ix++) {
-               fec->bdBase->rbd[ix].dataPointer = 
(u32)&fec->bdBase->recv_frames[ix];
+               fec->bdBase->rbd[ix].dataPointer =
+                               (u32)&fec->bdBase->recv_frames[ix];
                fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
                fec->bdBase->rbd[ix].dataLength = 0;
        }
@@ -118,8 +120,9 @@ static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, 
volatile FEC_RBD * pRb
 
        /*
         * Now, we have an empty RxBD, notify FEC
+        * Set Descriptor polling active
         */
-       fec->eth->r_des_active = 0x01000000;    /* Descriptor polling active */
+       out_be32(&fec->eth->r_des_active, 0x01000000);
 }
 
 /********************************************************************/
@@ -202,18 +205,20 @@ static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv 
*fec, char *mac)
         * Set individual hash table register
         */
        if (crc >= 32) {
-               fec->eth->iaddr1 = (1 << (crc - 32));
-               fec->eth->iaddr2 = 0;
+               out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
+               out_be32(&fec->eth->iaddr2, 0);
        } else {
-               fec->eth->iaddr1 = 0;
-               fec->eth->iaddr2 = (1 << crc);
+               out_be32(&fec->eth->iaddr1, 0);
+               out_be32(&fec->eth->iaddr2, (1 << crc));
        }
 
        /*
         * Set physical address
         */
-       fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + 
mac[3];
-       fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
+       out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
+                                   (mac[2] <<  8) + mac[3]);
+       out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
+                                    0x8808);
 }
 
 /********************************************************************/
@@ -226,45 +231,45 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t 
* bis)
 #endif
 
        /* Set interrupt mask register */
-       fec->eth->imask = 0x00000000;
+       out_be32(&fec->eth->imask, 0x00000000);
 
        /* Clear FEC-Lite interrupt event register(IEVENT) */
-       fec->eth->ievent = 0xffffffff;
+       out_be32(&fec->eth->ievent, 0xffffffff);
 
        /* Set transmit fifo watermark register(X_WMRK), default = 64 */
-       fec->eth->x_wmrk = 0x0;
+       out_be32(&fec->eth->x_wmrk, 0x0);
 
        /* Set Opcode/Pause Duration Register */
-       fec->eth->op_pause = 0x00010020;
+       out_be32(&fec->eth->op_pause, 0x00010020);
 
        /* Frame length=1522; MII mode */
-       fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
+       out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
 
        /* Half-duplex, heartbeat disabled */
-       fec->eth->x_cntrl = 0x00000000;
+       out_be32(&fec->eth->x_cntrl, 0x00000000);
 
        /* Enable MIB counters */
-       fec->eth->mib_control = 0x0;
+       out_be32(&fec->eth->mib_control, 0x0);
 
        /* Setup recv fifo start and buff size */
-       fec->eth->r_fstart = 0x500;
-       fec->eth->r_buff_size = FEC_BUFFER_SIZE;
+       out_be32(&fec->eth->r_fstart, 0x500);
+       out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
 
        /* Setup BD base addresses */
-       fec->eth->r_des_start = (u32)fec->bdBase->rbd;
-       fec->eth->x_des_start = (u32)fec->bdBase->tbd;
+       out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
+       out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
 
        /* DMA Control */
-       fec->eth->dma_control = 0xc0000000;
+       out_be32(&fec->eth->dma_control, 0xc0000000);
 
        /* Enable FEC */
-       fec->eth->ecntrl |= 0x00000006;
+       setbits_be32(&fec->eth->ecntrl, 0x00000006);
 
        /* Initilize addresses and status words of BDs */
        mpc512x_fec_bd_init (fec);
 
         /* Descriptor polling active */
-       fec->eth->r_des_active = 0x01000000;
+       out_be32(&fec->eth->r_des_active, 0x01000000);
 
 #if (DEBUG & 0x1)
        printf("mpc512x_fec_init... Done \n");
@@ -287,19 +292,20 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * 
bis)
        /*
         * Clear FEC-Lite interrupt event register(IEVENT)
         */
-       fec->eth->ievent = 0xffffffff;
+       out_be32(&fec->eth->ievent, 0xffffffff);
 
        /*
         * Set interrupt mask register
         */
-       fec->eth->imask = 0x00000000;
+       out_be32(&fec->eth->imask, 0x00000000);
 
        if (fec->xcv_type != SEVENWIRE) {
                /*
                 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
                 * and do not drop the Preamble.
                 */
-               fec->eth->mii_speed = (((gd->ips_clk / 1000000) / 5) + 1) << 1;
+               out_be32(&fec->eth->mii_speed,
+                        (((gd->ips_clk / 1000000) / 5) + 1) << 1);
 
                /*
                 * Reset PHY, then delay 300ns
@@ -413,27 +419,28 @@ static void mpc512x_fec_halt (struct eth_device *dev)
        /*
         * mask FEC chip interrupts
         */
-       fec->eth->imask = 0;
+       out_be32(&fec->eth->imask, 0);
 
        /*
         * issue graceful stop command to the FEC transmitter if necessary
         */
-       fec->eth->x_cntrl |= 0x00000001;
+       setbits_be32(&fec->eth->x_cntrl, 0x00000001);
 
        /*
         * wait for graceful stop to register
         */
-       while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
+       while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
+               ;
 
        /*
         * Disable the Ethernet Controller
         */
-       fec->eth->ecntrl &= 0xfffffffd;
+       clrbits_be32(&fec->eth->ecntrl, 0x00000002);
 
        /*
         * Issue a reset command to the FEC chip
         */
-       fec->eth->ecntrl |= 0x1;
+       setbits_be32(&fec->eth->ecntrl, 0x1);
 
        /*
         * wait at least 16 clock cycles
@@ -492,7 +499,7 @@ static int mpc512x_fec_send (struct eth_device *dev, 
volatile void *eth_data,
        fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
 
        /* Activate transmit Buffer Descriptor polling */
-       fec->eth->x_des_active = 0x01000000;    /* Descriptor polling active    
*/
+       out_be32(&fec->eth->x_des_active, 0x01000000);
 
 #if (DEBUG & 0x8)
        printf ( "+" );
@@ -535,8 +542,8 @@ static int mpc512x_fec_recv (struct eth_device *dev)
        /*
         * Check if any critical events have happened
         */
-       ievent = fec->eth->ievent;
-       fec->eth->ievent = ievent;
+       ievent = in_be32(&fec->eth->ievent);
+       out_be32(&fec->eth->ievent, ievent);
        if (ievent & 0x20060000) {
                /* BABT, Rx/Tx FIFO errors */
                mpc512x_fec_halt (dev);
@@ -545,13 +552,13 @@ static int mpc512x_fec_recv (struct eth_device *dev)
        }
        if (ievent & 0x80000000) {
                /* Heartbeat error */
-               fec->eth->x_cntrl |= 0x00000001;
+               setbits_be32(&fec->eth->x_cntrl, 0x00000001);
        }
        if (ievent & 0x10000000) {
                /* Graceful stop complete */
-               if (fec->eth->x_cntrl & 0x00000001) {
+               if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
                        mpc512x_fec_halt (dev);
-                       fec->eth->x_cntrl &= ~0x00000001;
+                       clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
                        mpc512x_fec_init (dev, NULL);
                }
        }
@@ -597,7 +604,8 @@ static int mpc512x_fec_recv (struct eth_device *dev)
        }
 
        /* Try to fill Buffer Descriptors */
-       fec->eth->r_des_active = 0x01000000;    /* Descriptor polling active */
+       out_be32(&fec->eth->r_des_active, 0x01000000);
+
        return frame_length;
 }
 
@@ -653,12 +661,12 @@ int mpc512x_fec_initialize (bd_t * bis)
        /*
         * Set interrupt mask register
         */
-       fec->eth->imask = 0x00000000;
+       out_be32(&fec->eth->imask, 0x00000000);
 
        /*
         * Clear FEC-Lite interrupt event register(IEVENT)
         */
-       fec->eth->ievent = 0xffffffff;
+       out_be32(&fec->eth->ievent, 0xffffffff);
 
        /*
         * Try to set the mac address now. The fec mac address is
@@ -673,8 +681,8 @@ int mpc512x_fec_initialize (bd_t * bis)
                                tmp = (*end) ? end+1 : end;
                }
                mpc512x_fec_set_hwaddr (fec, env_enetaddr);
-               fec->eth->gaddr1 = 0x00000000;
-               fec->eth->gaddr2 = 0x00000000;
+               out_be32(&fec->eth->gaddr1, 0x00000000);
+               out_be32(&fec->eth->gaddr2, 0x00000000);
        }
 
        mpc512x_fec_init_phy (dev, bis);
@@ -700,12 +708,16 @@ int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 
regAddr, u16 * retVal)
        reg = regAddr << FEC_MII_DATA_RA_SHIFT;
        phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-       eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA 
| phy | reg);
+       out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+                                FEC_MII_DATA_OP_RD |
+                                FEC_MII_DATA_TA |
+                                phy | reg);
 
        /*
         * wait for the related interrupt
         */
-       while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+       while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+               ;
 
        if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -717,12 +729,12 @@ int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 
regAddr, u16 * retVal)
        /*
         * clear mii interrupt bit
         */
-       eth->ievent = 0x00800000;
+       out_be32(&eth->ievent, 0x00800000);
 
        /*
         * it's now safe to read the PHY's register
         */
-       *retVal = (u16) eth->mii_data;
+       *retVal = (u16) in_be32(&eth->mii_data);
 
        return 0;
 }
@@ -740,13 +752,16 @@ int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 
regAddr, u16 data)
        reg = regAddr << FEC_MII_DATA_RA_SHIFT;
        phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
 
-       eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
-                       FEC_MII_DATA_TA | phy | reg | data);
+       out_be32(&eth->mii_data, FEC_MII_DATA_ST |
+                                FEC_MII_DATA_OP_WR |
+                                FEC_MII_DATA_TA |
+                                phy | reg | data);
 
        /*
         * wait for the MII interrupt
         */
-       while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
+       while ((timeout--) && (!(in_be32(&eth->ievent) & 0x00800000)))
+               ;
 
        if (timeout == 0) {
 #if (DEBUG & 0x2)
@@ -758,7 +773,7 @@ int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 
regAddr, u16 data)
        /*
         * clear MII interrupt bit
         */
-       eth->ievent = 0x00800000;
+       out_be32(&eth->ievent, 0x00800000);
 
        return 0;
 }
-- 
1.6.0.6

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 27/29] drivers/net/mpc512x_fec.c: use I/O accessors instead of pointer accesses

Reply via email to