Use existing struct fec512x instead.
Signed-off-by: Wolfgang Denk <w...@denx.de>
Cc: John Rigby <jcri...@gmail.com>
---
drivers/net/mpc512x_fec.c | 11 ++---
drivers/net/mpc512x_fec.h | 126 +--------------------------------------------
2 files changed, 5 insertions(+), 132 deletions(-)
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index fe28bdf..e683f98 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -613,7 +613,6 @@ static int mpc512x_fec_recv (struct eth_device *dev)
int mpc512x_fec_initialize (bd_t * bis)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec512x_t *fec512x = &im->fec;
mpc512x_fec_priv *fec;
struct eth_device *dev;
int i;
@@ -624,7 +623,7 @@ int mpc512x_fec_initialize (bd_t * bis)
dev = (struct eth_device *) malloc (sizeof(*dev));
memset (dev, 0, sizeof *dev);
- fec->eth = (ethernet_regs *)fec512x;
+ fec->eth = &im->fec;
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
@@ -632,7 +631,7 @@ int mpc512x_fec_initialize (bd_t * bis)
fec->xcv_type = MII10;
# endif
dev->priv = (void *)fec;
- dev->iobase = (int)fec512x;
+ dev->iobase = (int)&im->fec;
dev->init = mpc512x_fec_init;
dev->halt = mpc512x_fec_halt;
dev->send = mpc512x_fec_send;
@@ -695,8 +694,7 @@ int mpc512x_fec_initialize (bd_t * bis)
int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec512x_t *fec512x = &im->fec;
- ethernet_regs *eth = (ethernet_regs *)fec512x;
+ volatile fec512x_t *eth = &im->fec;
u32 reg; /* convenient holder for the PHY register */
u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
@@ -743,8 +741,7 @@ int fec512x_miiphy_read (char *devname, u8 phyAddr, u8
regAddr, u16 * retVal)
int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec512x_t *fec512x = &im->fec;
- ethernet_regs *eth = (ethernet_regs *)fec512x;
+ volatile fec512x_t *eth = &im->fec;
u32 reg; /* convenient holder for the PHY register */
u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
index 67c9b64..df25bf1 100644
--- a/drivers/net/mpc512x_fec.h
+++ b/drivers/net/mpc512x_fec.h
@@ -10,130 +10,6 @@
#include <common.h>
-typedef struct ethernet_register_set {
-
-/* [10:2]addr = 00 */
-
-/* Control and status Registers (offset 000-1FF) */
-
- volatile u32 fec_id; /* MBAR_ETH + 0x000 */
- volatile u32 ievent; /* MBAR_ETH + 0x004 */
- volatile u32 imask; /* MBAR_ETH + 0x008 */
-
- volatile u32 RES0[1]; /* MBAR_ETH + 0x00C */
- volatile u32 r_des_active; /* MBAR_ETH + 0x010 */
- volatile u32 x_des_active; /* MBAR_ETH + 0x014 */
-
- volatile u32 RES1[3]; /* MBAR_ETH + 0x018-020 */
- volatile u32 ecntrl; /* MBAR_ETH + 0x024 */
-
- volatile u32 RES2[6]; /* MBAR_ETH + 0x028-03C */
- volatile u32 mii_data; /* MBAR_ETH + 0x040 */
- volatile u32 mii_speed; /* MBAR_ETH + 0x044 */
-
- volatile u32 RES3[7]; /* MBAR_ETH + 0x048-060 */
- volatile u32 mib_control; /* MBAR_ETH + 0x064 */
-
- volatile u32 RES4[7]; /* MBAR_ETH + 0x068-80 */
- volatile u32 r_cntrl; /* MBAR_ETH + 0x084 */
- volatile u32 r_hash; /* MBAR_ETH + 0x088 */
-
- volatile u32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */
- volatile u32 x_cntrl; /* MBAR_ETH + 0x0C4 */
-
- volatile u32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */
- volatile u32 paddr1; /* MBAR_ETH + 0x0E4 */
- volatile u32 paddr2; /* MBAR_ETH + 0x0E8 */
- volatile u32 op_pause; /* MBAR_ETH + 0x0EC */
-
- volatile u32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */
- volatile u32 iaddr1; /* MBAR_ETH + 0x118 */
- volatile u32 iaddr2; /* MBAR_ETH + 0x11C */
- volatile u32 gaddr1; /* MBAR_ETH + 0x120 */
- volatile u32 gaddr2; /* MBAR_ETH + 0x124 */
-
- volatile u32 RES8[6]; /* MBAR_ETH + 0x128-13C */
- volatile u32 fifo_id; /* MBAR_ETH + 0x140 */
- volatile u32 x_wmrk; /* MBAR_ETH + 0x144 */
- volatile u32 RES9[1]; /* MBAR_ETH + 0x148 */
- volatile u32 r_bound; /* MBAR_ETH + 0x14C */
- volatile u32 r_fstart; /* MBAR_ETH + 0x150 */
-
- volatile u32 RES10[11]; /* MBAR_ETH + 0x154-17C */
- volatile u32 r_des_start; /* MBAR_ETH + 0x180 */
- volatile u32 x_des_start; /* MBAR_ETH + 0x184 */
- volatile u32 r_buff_size; /* MBAR_ETH + 0x188 */
- volatile u32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */
- volatile u32 dma_control; /* MBAR_ETH + 0x1F4 */
- volatile u32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */
-
-/* MIB COUNTERS (Offset 200-2FF) */
-
- volatile u32 rmon_t_drop; /* MBAR_ETH + 0x200 */
- volatile u32 rmon_t_packets; /* MBAR_ETH + 0x204 */
- volatile u32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
- volatile u32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
- volatile u32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
- volatile u32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
- volatile u32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
- volatile u32 rmon_t_frag; /* MBAR_ETH + 0x21C */
- volatile u32 rmon_t_jab; /* MBAR_ETH + 0x220 */
- volatile u32 rmon_t_col; /* MBAR_ETH + 0x224 */
- volatile u32 rmon_t_p64; /* MBAR_ETH + 0x228 */
- volatile u32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
- volatile u32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
- volatile u32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
- volatile u32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
- volatile u32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
- volatile u32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
- volatile u32 rmon_t_octets; /* MBAR_ETH + 0x244 */
- volatile u32 ieee_t_drop; /* MBAR_ETH + 0x248 */
- volatile u32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
- volatile u32 ieee_t_1col; /* MBAR_ETH + 0x250 */
- volatile u32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
- volatile u32 ieee_t_def; /* MBAR_ETH + 0x258 */
- volatile u32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
- volatile u32 ieee_t_excol; /* MBAR_ETH + 0x260 */
- volatile u32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
- volatile u32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
- volatile u32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
- volatile u32 t_fdxfc; /* MBAR_ETH + 0x270 */
- volatile u32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
-
- volatile u32 RES13[2]; /* MBAR_ETH + 0x278-27C */
- volatile u32 rmon_r_drop; /* MBAR_ETH + 0x280 */
- volatile u32 rmon_r_packets; /* MBAR_ETH + 0x284 */
- volatile u32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
- volatile u32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
- volatile u32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
- volatile u32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
- volatile u32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
- volatile u32 rmon_r_frag; /* MBAR_ETH + 0x29C */
- volatile u32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
-
- volatile u32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
-
- volatile u32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
- volatile u32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
- volatile u32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
- volatile u32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
- volatile u32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
- volatile u32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
- volatile u32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
- volatile u32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
- volatile u32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
- volatile u32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
- volatile u32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
- volatile u32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
- volatile u32 r_macerr; /* MBAR_ETH + 0x2D8 */
- volatile u32 r_fdxfc; /* MBAR_ETH + 0x2DC */
- volatile u32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
-
- volatile u32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */
-
- volatile u32 RES15[64]; /* MBAR_ETH + 0x300-3FF */
-} ethernet_regs;
-
/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
u16 status;
@@ -175,7 +51,7 @@ typedef struct {
} mpc512x_buff_descs;
typedef struct {
- ethernet_regs *eth;
+ volatile fec512x_t *eth;
xceiver_type xcv_type; /* transceiver type */
mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
u16 rbdIndex; /* next receive BD to read */
--
1.6.0.6
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