On 09/15/2014 06:06 AM, Marek Vasut wrote:
> The inlining is done by GCC whe needed, there is no need to do it
s/whe/when.
Acked-by: Dinh Nguyen <dingu...@opensource.altera.com>
thanks...
> explicitly. Furthermore, the inline keyword does not force-inline
> the code, but is only a hint for the compiler. Scrub this hint.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Chin Liang See <cl...@altera.com>
> Cc: Dinh Nguyen <dingu...@altera.com>
> Cc: Albert Aribaud <albert.u.b...@aribaud.net>
> Cc: Tom Rini <tr...@ti.com>
> Cc: Wolfgang Denk <w...@denx.de>
> Cc: Pavel Machek <pa...@denx.de>
> ---
> arch/arm/cpu/armv7/socfpga/clock_manager.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c
> b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> index 158501a..d032bbd 100644
> --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
> +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
> @@ -30,7 +30,7 @@ static const struct socfpga_clock_manager
> *clock_manager_base =
> CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
> CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
>
> -static inline void cm_wait_for_lock(uint32_t mask)
> +static void cm_wait_for_lock(uint32_t mask)
> {
> register uint32_t inter_val;
> do {
> @@ -39,7 +39,7 @@ static inline void cm_wait_for_lock(uint32_t mask)
> }
>
> /* function to poll in the fsm busy bit */
> -static inline void cm_wait_for_fsm(void)
> +static void cm_wait_for_fsm(void)
> {
> while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
> ;
> @@ -49,22 +49,22 @@ static inline void cm_wait_for_fsm(void)
> * function to write the bypass register which requires a poll of the
> * busy bit
> */
> -static inline void cm_write_bypass(uint32_t val)
> +static void cm_write_bypass(uint32_t val)
> {
> writel(val, &clock_manager_base->bypass);
> cm_wait_for_fsm();
> }
>
> /* function to write the ctrl register which requires a poll of the busy bit
> */
> -static inline void cm_write_ctrl(uint32_t val)
> +static void cm_write_ctrl(uint32_t val)
> {
> writel(val, &clock_manager_base->ctrl);
> cm_wait_for_fsm();
> }
>
> /* function to write a clock register that has phase information */
> -static inline void cm_write_with_phase(uint32_t value,
> - uint32_t reg_address, uint32_t mask)
> +static void cm_write_with_phase(uint32_t value,
> + uint32_t reg_address, uint32_t mask)
> {
> /* poll until phase is zero */
> while (readl(reg_address) & mask)
>
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