On 09/16/2014 12:12 PM, Marek Vasut wrote: > On Tuesday, September 16, 2014 at 11:42:00 AM, Michal Simek wrote: >> On 09/15/2014 01:06 PM, Marek Vasut wrote: >>> From: Pavel Machek <pa...@denx.de> >>> >>> Add code necessary to program the FPGA part of SoCFPGA from U-Boot >>> with an RBF blob. This patch also integrates the code into the >>> FPGA driver framework in U-Boot so it can be used via the 'fpga' >>> command. >>> >>> Signed-off-by: Pavel Machek <pa...@denx.de> >>> Signed-off-by: Marek Vasut <ma...@denx.de> >>> Cc: Chin Liang See <cl...@altera.com> >>> Cc: Dinh Nguyen <dingu...@altera.com> >>> Cc: Albert Aribaud <albert.u.b...@aribaud.net> >>> Cc: Tom Rini <tr...@ti.com> >>> Cc: Wolfgang Denk <w...@denx.de> >>> Cc: Pavel Machek <pa...@denx.de> >>> --- >>> >>> arch/arm/cpu/armv7/socfpga/Makefile | 3 +- >>> arch/arm/cpu/armv7/socfpga/fpga_manager.c | 354 >>> +++++++++++++++++++++++ >> >> We have drivers/fpga and you should move this driver there to be visible >> for others. Maybe also nios can use this driver with some changes. > > Good point about the move, but how could NIOS possibly use this ?
I don't know the architecture but I expect that this fpga_manager can also work with partial bitstream. It means the flow is. 1. load full bitstream with NIOS 2. NIOS become security manager and own this driver 3. NIOS is able to load partial bitstreams via this device. Not sure if this realistic flow on socfpga but this is possible to do on our fpga. That's why IMHO this driver should be in drivers/fpga. Also look at my xilinx fpga changes I have done recently and you should change that altera code to look the same and remove that ugly ifdef mess. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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