Unlike regular OMAP5, on the DRA7xx SoCs the I2C5 module belongs to
the IPU clock domain. This patch takes care of the appropriate clock
preparation and makes I2C5 operational - it fixes the 'data abort'
exception that otherwise happened upon accessing the I2C5 controller.

Signed-off-by: Lubomir Popov <l-po...@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c   |    9 +++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c |    4 ++++
 arch/arm/include/asm/omap_common.h   |    4 ++++
 3 files changed, 17 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c 
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0257383..5f7b392 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -515,6 +515,10 @@ void enable_basic_clocks(void)
 void enable_basic_uboot_clocks(void)
 {
        u32 const clk_domains_essential[] = {
+#ifdef CONFIG_DRA7XX
+               /* Needed for I2C5 operation */
+               (*prcm)->cm_ipu_clkstctrl,
+#endif
                0
        };

@@ -528,7 +532,12 @@ void enable_basic_uboot_clocks(void)
                (*prcm)->cm_l4per_i2c2_clkctrl,
                (*prcm)->cm_l4per_i2c3_clkctrl,
                (*prcm)->cm_l4per_i2c4_clkctrl,
+#ifdef CONFIG_DRA7XX
+               /* I2C5 is in the IPU clock domain on the DRA7xx */
+               (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
                (*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
                (*prcm)->cm_l3init_hsusbhost_clkctrl,
                (*prcm)->cm_l3init_fsusb_clkctrl,
                0
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c 
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index ff08ef4..1337198 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -808,6 +808,10 @@ struct prcm_regs const dra7xx_prcm = {
        /* cm1.dsp */
        .cm_dsp_clkstctrl                       = 0x4a005400,
        .cm_dsp_dsp_clkctrl                     = 0x4a005420,
+
+       /* cm1.ipu */
+       .cm_ipu_clkstctrl                       = 0x4a005540,
+       .cm_ipu_i2c5_clkctrl                    = 0x4a005578,

        /* prm irqstatus regs */
        .prm_irqstatus_mpu_2                    = 0x4ae06014,
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index 1838234..962c8a5 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -80,6 +80,10 @@ struct prcm_regs {
        u32 cm_dsp_clkstctrl;
        u32 cm_dsp_dsp_clkctrl;

+       /* cm1.ipu */
+       u32 cm_ipu_clkstctrl;
+       u32 cm_ipu_i2c5_clkctrl;
+
        /* cm1.abe */
        u32 cm1_abe_clkstctrl;
        u32 cm1_abe_l4abe_clkctrl;
-- 
1.7.9.5

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Reply via email to