On Wed, Mar 11, 2015 at 08:12:12PM +0000, Fabio Estevam wrote: > From: Fabio Estevam <fabio.este...@freescale.com> > > Having bit 22 cleared in the PL310 Auxiliary Control register (shared > attribute override enable) has the side effect of transforming Normal > Shared Non-cacheable reads into Cacheable no-allocate reads. > > Coherent DMA buffers in Linux always have a Cacheable alias via the > kernel linear mapping and the processor can speculatively load cache > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > reads would unexpectedly hit such cache lines leading to buffer > corruption. > > This was inspired by a patch from Catalin Marinas [1] and also from recent > discussions in the linux-arm-kernel list [2] where Russell King and Rob > Herring > suggested that bootloaders should initialize the cache. > > [1] > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html > [2] https://lkml.org/lkml/2015/2/20/199 > > Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
Acked-by: Catalin Marinas <catalin.mari...@arm.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
