On Wed, Mar 11, 2015 at 05:12:12PM -0300, Fabio Estevam wrote: > From: Fabio Estevam <fabio.este...@freescale.com> > > Having bit 22 cleared in the PL310 Auxiliary Control register (shared > attribute override enable) has the side effect of transforming Normal > Shared Non-cacheable reads into Cacheable no-allocate reads. > > Coherent DMA buffers in Linux always have a Cacheable alias via the > kernel linear mapping and the processor can speculatively load cache > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > reads would unexpectedly hit such cache lines leading to buffer > corruption. > > This was inspired by a patch from Catalin Marinas [1] and also from recent > discussions in the linux-arm-kernel list [2] where Russell King and Rob > Herring > suggested that bootloaders should initialize the cache. > > [1] > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html > [2] https://lkml.org/lkml/2015/2/20/199 > > Signed-off-by: Fabio Estevam <fabio.este...@freescale.com> > --- > arch/arm/cpu/armv7/mx6/soc.c | 8 ++++++++ > arch/arm/include/asm/pl310.h | 2 ++ > 2 files changed, 10 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index ef02972..5aab305 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -506,6 +506,14 @@ void v7_outer_cache_enable(void) > struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; > unsigned int val; > > + > + /* > + * Set bit 22 in the auxiliary control register. If this bit > + * is cleared, PL310 treats Normal Shared Non-cacheable > + * accesses as Cacheable no-allocate. > + */ > + setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); > + > #if defined CONFIG_MX6SL > struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; > val = readl(&iomux->gpr[11]);
We should put this somewhere a bit more common that other A9 cores can also call into like OMAP4, SoCFPGA and maybe zynq later (based on a quick git grep pl310). -- Tom
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