The DIGPROG register map:
23 ------- 16 | 15 ------ 8 | 7 --- 0 |
Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li <b37...@freescale.com>
Signed-off-by: Peng Fan <peng....@freescale.com>
---
Changes v2:
split from PATCH v1 2/8. This piece code should be in a single patch.
arch/arm/cpu/armv7/mx6/soc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index b21bd03..29de624 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -62,6 +62,7 @@ u32 get_cpu_rev(void)
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->digprog_sololite);
u32 type = ((reg >> 16) & 0xff);
+ u32 major;
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
@@ -79,8 +80,9 @@ u32 get_cpu_rev(void)
}
}
+ major = ((reg >> 8) & 0xff);
reg &= 0xff; /* mx6 silicon revision */
- return (type << 12) | (reg + 0x10);
+ return (type << 12) | (reg + (0x10 * (major + 1)));
}
/*
--
1.8.4
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