The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Bypass QoS for IPU and increase bankwidth threshold for PRE to get
better performance for video.
Signed-off-by: Peng Fan <peng....@freescale.com>
Signed-off-by: Brown Oliver <b37...@freescale.com>
Signed-off-by: Ye.Li <b37...@freescale.com>
---
Changes v2:
1. runtime check
2. introduce ipu qos settings for better performance
arch/arm/cpu/armv7/mx6/clock.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 0d862b2..7106df0 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -862,6 +862,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
}
#ifndef CONFIG_MX6SX
+static void ipu_qos_setting(void)
+{
+ /* Bypass IPU1 QoS generator */
+ writel(0x00000002, 0x00bb048c);
+ /* Bypass IPU2 QoS generator */
+ writel(0x00000002, 0x00bb050c);
+ /* Bandwidth THR for of PRE0 */
+ writel(0x00000200, 0x00bb0690);
+ /* Bandwidth THR for of PRE1 */
+ writel(0x00000200, 0x00bb0710);
+ /* Bandwidth THR for of PRE2 */
+ writel(0x00000200, 0x00bb0790);
+ /* Bandwidth THR for of PRE3 */
+ writel(0x00000200, 0x00bb0810);
+ /* Saturation THR for of PRE0 */
+ writel(0x00000010, 0x00bb0694);
+ /* Saturation THR for of PRE1 */
+ writel(0x00000010, 0x00bb0714);
+ /* Saturation THR for of PRE2 */
+ writel(0x00000010, 0x00bb0794);
+ /* Saturation THR for of PRE */
+ writel(0x00000010, 0x00bb0814);
+}
+
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -869,7 +893,22 @@ void enable_ipu_clock(void)
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
+
+ if (is_mx6dqp()) {
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
+ reg = readl(&mxc_ccm->CCGR6);
+ reg |= MXC_CCM_CCGR6_PRG_CLK0_MASK;
+ writel(reg, &mxc_ccm->CCGR6);
+
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* See Network Interconnect Bus for detailed info */
+ ipu_qos_setting();
+ }
}
+
#endif
/***************************************************/
--
1.8.4
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