* Add imx7d support for iomux controller * Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins.
Signed-off-by: Adrian Alonso <aalo...@freescale.com> Signed-off-by: Fugang Duan <b38...@freescale.com> Signed-off-by: Ye.Li <b37...@freescale.com> --- arch/arm/imx-common/iomux-v3.c | 20 ++++++++++++++++++- arch/arm/include/asm/imx-common/iomux-v3.h | 32 ++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fb23dd..07e75a6 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * <armli...@phytec.de> * - * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) } #endif +#ifdef CONFIG_IOMUX_LPSR + u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; + + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_LPSR_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + /* set daisy chain sel_input */ + if (sel_input_ofs) + sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); @@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); #endif + +#ifdef CONFIG_IOMUX_LPSR + if (lpsr == IOMUX_CONFIG_LPSR) + base = (void *)IOMUXC_BASE_ADDR; +#endif + } /* configures a list of pads within declared with IOMUX_PADS macro */ diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 2581019..5dd64f5 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t; #define NO_PAD_CTRL (1 << 17) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 +#define IOMUX_CONFIG_LPSR 0x8 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else + #ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16) @@ -167,6 +197,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_SLOW (0 << 0) #define PAD_CTL_SRE_FAST (1 << 0) +#endif + #define IOMUX_CONFIG_SION 0x10 #define GPIO_PIN_MASK 0x1f -- 2.1.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot