On 03/21/2016 09:16 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
Hi!
> I solved the Ethernet problem on our board.
>
> The problem was in the register below:
>
> Link:
> http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
> Registers used by the EMACs. All fields are reset by a cold or warm reset.
> Module Instance Base Address Register Address
> sysmgr 0xFFD08000 0xFFD08060
Thanks for looking into it, try if the attached patch works for you.
Make sure you have correct phy-mode = "gmii"; DT node specified for
the GMAC you use, Arria V SoCDK surely uses phy-mode = "rgmii";
> I found that difference while comparing the dumps between OK and NOK cases.
>
> In new U-Boot (2016) the values of
> ctrl :: physel_0
> ctrl :: physel_1
> were always set to
> 0x1 Select RGMII PHY interface
>
> I changed this value to
> 0x0 Select GMII/MII PHY interface
[...]
> But still I have this sort of question:
> Why those two registers are always assigned to RGMII PHY interface (and
> default value is 0x2 Select RMII PHY interface)?
> In current code there is no way to change this value.
Most likely because noone ever had a board with PHY connected over
anything else but RGMII, so this went unnoticed.
> I changed it like this:
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> old mode 100644
> new mode 100755
> index 9b43b92..295ed5a
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -23,6 +23,8 @@
>
> @@ -97,14 +99,19 @@ static void dwmac_deassert_reset(const unsigned int
> of_reset_id)
> SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
>
> /* configure to PHY interface select choosed */
> +#ifdef CONFIG_WORKAROUND
> + setbits_le32(&sysmgr_regs->emacgrp_ctrl,
> + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << physhift);
> +#else
> setbits_le32(&sysmgr_regs->emacgrp_ctrl,
> SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
> +#endif
>
> /* Release the EMAC controller from reset */
> socfpga_per_reset(reset, 0);
> }
>
> Please evaluate my correction.
> Maybe we can assign ctrl :: physel_0 and ctrl :: physel_1 based on some
> switch in config?
We should parse the OF node phy-mode, which describes which mode your
PHY uses. If your DT is written correctly, then with the attached patch,
any PHY mode should work.
> Best regards,
> Denis Bakhvalov
>
--
Best regards,
Marek Vasut
>From 7dff237a37fe9585613c5bdab597b18bc3e1daa5 Mon Sep 17 00:00:00 2001
From: Marek Vasut <ma...@denx.de>
Date: Mon, 21 Mar 2016 12:06:47 +0100
Subject: [PATCH] arm: socfpga: Handle phy-mode OF property for GMACs
Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.
This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
Signed-off-by: Marek Vasut <ma...@denx.de>
Reported-by: Denis Bakhvalov <denis.bakhva...@nokia.com>
Cc: Dinh Nguyen <dingu...@opensource.altera.com>
---
arch/arm/mach-socfpga/misc.c | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0a..5f988e3 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -77,7 +77,8 @@ void v7_outer_cache_disable(void)
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+ const u32 phymode)
{
u32 physhift, reset;
@@ -98,16 +99,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
/* configure to PHY interface select choosed */
setbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+ phymode << physhift);
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+ if (!phymode)
+ return -EINVAL;
+
+ if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rgmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ return 0;
+ }
+
+ if (!strcmp(phymode, "rmii")) {
+ *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
static int socfpga_eth_reset(void)
{
const void *fdt = gd->fdt_blob;
struct fdtdec_phandle_args args;
+ const char *phy_mode;
+ u32 phy_modereg;
int nodes[2]; /* Max. two GMACs */
int ret, count;
int i, node;
@@ -132,7 +158,14 @@ static int socfpga_eth_reset(void)
continue;
}
- dwmac_deassert_reset(args.args[0]);
+ phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+ ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+ if (ret) {
+ debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+ continue;
+ }
+
+ dwmac_deassert_reset(args.args[0], phy_modereg);
}
return 0;
--
2.7.0
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