Hi, On Wednesday 02 November 2016 08:45 PM, Phil Edworthy wrote: > The HW manual does not give details about what the register > value for this bit actually does, other than "Choose edge on > which data outputs from flash memory will be sampled". > > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> > > --- > Our HW engineers tell me that it needs to be set for our hardware. > --- > doc/device-tree-bindings/spi/spi-cadence.txt | 2 ++ > drivers/spi/cadence_qspi.c | 10 +++++++--- > drivers/spi/cadence_qspi.h | 3 ++- > drivers/spi/cadence_qspi_apb.c | 8 +++++++- > 4 files changed, 18 insertions(+), 5 deletions(-) > > diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt > b/doc/device-tree-bindings/spi/spi-cadence.txt > index c1e2233..71aa06a 100644 > --- a/doc/device-tree-bindings/spi/spi-cadence.txt > +++ b/doc/device-tree-bindings/spi/spi-cadence.txt > @@ -26,3 +26,5 @@ connected flash properties > select (n_ss_out). > - tslch-ns : Delay in master reference clocks between setting > n_ss_out low and first bit transfer > +- sample-edge : The edge on which data outputs from flash > memory will > + be sampled.
Could this be changed to bool property say sample-edge-rising? sample-edge-rising(optional): data outputs from flash memory will be sampled at the rising edge. Default is falling edge -- Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot