On 25.2.2017 22:44, Marek Vasut wrote: > On 02/22/2017 10:47 AM, Ley Foon Tan wrote: >> Arria 10 SPL needs the drivers/fpga. >> >> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> >> Signed-off-by: Ley Foon Tan <ley.foon....@intel.com> >> --- >> drivers/Makefile | 1 + > > +CC Michal and Moritz, they did some FPGA/SPL work too. > >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/Makefile b/drivers/Makefile >> index 34c55bf..6e7a2c3 100644 >> --- a/drivers/Makefile >> +++ b/drivers/Makefile >> @@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ >> obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ >> obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ >> obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ >> +obj-$(CONFIG_FPGA) += fpga/ >> endif >> >> ifdef CONFIG_TPL_BUILD >> > >
I prefer if you can separate these fpga stuff out of this huge series. This patch doesn't make sense without content. I can't see that code which requires this. The biggest questions here are where are you calling fpga code and where are you taking bitstream from? Thanks, Michal _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/listinfo/u-boot
