From: Stefan Chulski <stef...@marvell.com> MVPP22 driver support 64 Bit arch and require BM pool high address configuration.
Change-Id: I04417b8cc081ea75e43b230d5ba1cc5c0071ce25 Signed-off-by: Stefan Chulski <stef...@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39967 Tested-by: iSoC Platform CI <ykj...@marvell.com> Reviewed-by: Nadav Haklai <nad...@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39953 Reviewed-by: Igal Liberman <ig...@marvell.com> --- drivers/net/mvpp2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 2cdf934..931047e 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -322,6 +322,8 @@ do { \ #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 #define MVPP22_BM_MC_RLS_REG 0x64d4 +#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310 +#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff /* TX Scheduler registers */ #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 @@ -2602,6 +2604,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev, mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), lower_32_bits(bm_pool->dma_addr)); + if (priv->hw_version == MVPP22) + mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG, + (upper_32_bits(bm_pool->dma_addr) & + MVPP22_BM_POOL_BASE_HIGH_MASK)); mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
