Hi Andy, On Thu, Jul 6, 2017 at 4:56 AM, Andy Shevchenko <andriy.shevche...@linux.intel.com> wrote: > Add Intel Edison board which is using U-Boot. > > The patch is based on work done by the following people (in alphabetical > order): > Aiden Park <aiden.p...@intel.com> > Dukjoon Jeon <dukjoon.j...@intel.com> > eric.park <eric.p...@intel.com> > Fabien Chereau <fabien.cher...@intel.com> > Felipe Balbi <felipe.ba...@linux.intel.com> > Scott D Phillips <scott.d.phill...@intel.com> > Sebastien Colleur <sebastienx.coll...@intel.com> > Steve Sakoman <steve.sako...@intel.com> > Vincent Tinelli <vincent.tine...@intel.com> > > In case we're building for Intel Edison, we must have 4096 bytes of > zeroes in the beginning on u-boot.bin. This is done in > board/intel/edison/config.mk. > > First run sets hardware_id environment variable which is read from > System Controller Unit (SCU). > > Serial number (serial# environment variable) is generated based on eMMC > CID. > > MAC address on USB network interface is unique to the board but kept the > same all over the time. > > Set mac address from U-Boot using following scheme: > OUI = 02:00:86 > next 3 bytes of MAC address set from eMMC serial number > > This allows to have a unique mac address across reboot and flashing. > > Signed-off-by: Vincent Tinelli <vincent.tine...@intel.com> > Signed-off-by: Felipe Balbi <felipe.ba...@linux.intel.com> > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com> > --- > arch/x86/cpu/tangier/Kconfig | 4 ++ > arch/x86/dts/Makefile | 1 + > arch/x86/dts/edison.dts | 89 ++++++++++++++++++++++++++++++++ > board/intel/Kconfig | 8 +++ > board/intel/edison/Kconfig | 26 ++++++++++ > board/intel/edison/Makefile | 1 + > board/intel/edison/config.mk | 18 +++++++ > board/intel/edison/edison.c | 104 > ++++++++++++++++++++++++++++++++++++++ > board/intel/edison/edison_start.S | 13 +++++ > configs/edison_defconfig | 53 +++++++++++++++++++ > doc/README.x86 | 39 ++++++++++++++ > include/configs/edison.h | 78 ++++++++++++++++++++++++++++ > 12 files changed, 434 insertions(+) > create mode 100644 arch/x86/dts/edison.dts > create mode 100644 board/intel/edison/Kconfig > create mode 100644 board/intel/edison/Makefile > create mode 100644 board/intel/edison/config.mk > create mode 100644 board/intel/edison/edison.c > create mode 100644 board/intel/edison/edison_start.S > create mode 100644 configs/edison_defconfig > create mode 100644 include/configs/edison.h >
Thank you for your efforts to bring edition support upstream! Looks quite clean. A few comments below. > diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig > index 92d3352f3b..b67c6a799e 100644 > --- a/arch/x86/cpu/tangier/Kconfig > +++ b/arch/x86/cpu/tangier/Kconfig > @@ -18,3 +18,7 @@ config SYS_CAR_SIZE > help > Space in bytes in eSRAM used as Cache-As-RAM (CAR). > Note this size must not exceed eSRAM's total size. > + > +config SYS_USB_OTG_BASE > + hex > + default 0xf9100000 Can this otg controller be put into device tree, like other peripherals? > diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile > index 3f534ad40a..6589495f23 100644 > --- a/arch/x86/dts/Makefile > +++ b/arch/x86/dts/Makefile > @@ -10,6 +10,7 @@ dtb-y += bayleybay.dtb \ > cougarcanyon2.dtb \ > crownbay.dtb \ > dfi-bt700-q7x-151.dtb \ > + edison.dtb \ > efi.dtb \ > galileo.dtb \ > minnowmax.dtb \ > diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts > new file mode 100644 > index 0000000000..0b04984c6e > --- /dev/null > +++ b/arch/x86/dts/edison.dts > @@ -0,0 +1,89 @@ > +/* > + * Copyright (c) 2017 Intel Corporation > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/gpio/x86-gpio.h> > +#include <dt-bindings/interrupt-router/intel-irq.h> > + > +/include/ "skeleton.dtsi" > +/include/ "rtc.dtsi" > +/include/ "tsc_timer.dtsi" > + > +/ { > + model = "Intel Edison"; > + compatible = "intel,edison"; > + > + aliases { > + serial0 = &serial0; > + }; > + > + chosen { > + stdout-path = &serial0; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "cpu-x86"; > + reg = <0>; > + intel,apic-id = <0>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "cpu-x86"; > + reg = <1>; > + intel,apic-id = <2>; > + }; > + }; > + > + pci { > + compatible = "pci-x86"; > + #address-cells = <3>; > + #size-cells = <2>; > + u-boot,dm-pre-reloc; > + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 > + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 > + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; > + }; > + > + serial0: serial@ff010180 { > + compatible = "intel,mid-uart"; > + reg = <0xff010180 0x100>; > + reg-shift = <0>; > + clock-frequency = <29491200>; > + current-speed = <115200>; > + }; > + > + emmc: mmc@ff3fc000 { > + compatible = "intel,sdhci-tangier"; > + reg = <0xff3fc000 0x1000>; > + }; > + > +/* > + * FIXME: For now U-Boot DM model doesn't allow to power up this controller. > + * Enabling it will make U-Boot hang. > + * > + sdcard: mmc@ff3fa000 { > + compatible = "intel,sdhci-tangier"; > + reg = <0xff3fa000 0x1000>; > + }; > + */ > + > + pmu: power@ff00b000 { > + compatible = "intel,pmu-mid"; > + reg = <0xff00b000 0x1000>; > + }; > + > + scu: ipc@ff009000 { > + compatible = "intel,scu-ipc"; > + reg = <0xff009000 0x1000>; > + }; > +}; > diff --git a/board/intel/Kconfig b/board/intel/Kconfig > index 4d341aa799..d7d950e877 100644 > --- a/board/intel/Kconfig > +++ b/board/intel/Kconfig > @@ -35,6 +35,13 @@ config TARGET_CROWNBAY > Intel Platform Controller Hub EG20T, other system components and > peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. > > +config TARGET_EDISON > + bool "Edison" > + help > + This is the Intel Edison Compute Module. It contains a dual core > Intel > + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB > + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. > + > config TARGET_GALILEO > bool "Galileo" > help > @@ -64,6 +71,7 @@ endchoice > source "board/intel/bayleybay/Kconfig" > source "board/intel/cougarcanyon2/Kconfig" > source "board/intel/crownbay/Kconfig" > +source "board/intel/edison/Kconfig" > source "board/intel/galileo/Kconfig" > source "board/intel/minnowmax/Kconfig" > > diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig > new file mode 100644 > index 0000000000..4ff9d5adec > --- /dev/null > +++ b/board/intel/edison/Kconfig > @@ -0,0 +1,26 @@ > +if TARGET_EDISON > + > +config SYS_BOARD > + default "edison" > + > +config SYS_VENDOR > + default "intel" > + > +config SYS_SOC > + default "tangier" > + > +config SYS_CONFIG_NAME > + default "edison" > + > +config SYS_TEXT_BASE > + default 0x01101000 > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select X86_LOAD_FROM_32_BIT > + select INTEL_MID > + select INTEL_TANGIER > + select BOARD_LATE_INIT > + select MD5 > + > +endif > diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile > new file mode 100644 > index 0000000000..a29f51294b > --- /dev/null > +++ b/board/intel/edison/Makefile > @@ -0,0 +1 @@ > +obj-y += edison_start.o edison.o > diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk > new file mode 100644 > index 0000000000..465133fd77 > --- /dev/null > +++ b/board/intel/edison/config.mk > @@ -0,0 +1,18 @@ > +# > +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. > +# Copyright (c) 2017 Intel Corporation > +# > +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause > +# > + > +# Add 4096 bytes of zeroes to u-boot.bin > +quiet_cmd_mkalign_eds = EDSALGN $@ > +cmd_mkalign_eds = \ > + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ > + mv $@ $^ > + > +ALL-y += u-boot-align.bin > +u-boot-align.bin: u-boot.bin > + $(call if_changed,mkalign_eds) > + > +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros > diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c > new file mode 100644 > index 0000000000..a1a7d4d7c8 > --- /dev/null > +++ b/board/intel/edison/edison.c > @@ -0,0 +1,104 @@ > +/* > + * Copyright (c) 2017 Intel Corporation > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#include <common.h> > +#include <dwc3-uboot.h> > +#include <mmc.h> > +#include <u-boot/md5.h> > +#include <usb.h> > +#include <watchdog.h> > + > +#include <linux/usb/gadget.h> > + > +#include <asm/cache.h> > +#include <asm/scu.h> > +#include <asm/u-boot-x86.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static struct dwc3_device dwc3_device_data = { > + .maximum_speed = USB_SPEED_HIGH, > + .base = CONFIG_SYS_USB_OTG_BASE, > + .dr_mode = USB_DR_MODE_PERIPHERAL, > + .index = 0, > +}; > + > +int usb_gadget_handle_interrupts(int controller_index) > +{ > + dwc3_uboot_handle_interrupt(controller_index); > + WATCHDOG_RESET(); > + return 0; > +} > + > +int board_usb_init(int index, enum usb_init_type init) > +{ > + if (index == 0 && init == USB_INIT_DEVICE) > + return dwc3_uboot_init(&dwc3_device_data); > + return -EINVAL; > +} > + > +int board_usb_cleanup(int index, enum usb_init_type init) > +{ > + if (index == 0 && init == USB_INIT_DEVICE) { > + dwc3_uboot_exit(index); > + return 0; > + } > + return -EINVAL; > +} > + > +static void assign_serial(void) > +{ > + struct mmc *mmc = find_mmc_device(0); > + unsigned char ssn[16]; > + char usb0addr[18]; > + char serial[33]; > + int i; > + > + if (!mmc) > + return; > + > + md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn); > + > + snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x", > + ssn[13], ssn[14], ssn[15]); > + setenv("usb0addr", usb0addr); > + > + for (i = 0; i < 16; i++) > + snprintf(&serial[2 * i], 3, "%02x", ssn[i]); > + setenv("serial#", serial); > + > +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) > + saveenv(); > +#endif > +} > + > +static void assign_hardware_id(void) > +{ > + struct ipc_ifwi_version v; > + char hardware_id[4]; > + int ret; > + > + ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, > 4); > + if (ret < 0) > + printf("Can't retrieve hardware revision\n"); > + > + snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id); > + setenv("hardware_id", hardware_id); > + > +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) > + saveenv(); > +#endif > +} > + > +int board_late_init(void) > +{ > + if (!getenv("serial#")) > + assign_serial(); > + > + if (!getenv("hardware_id")) > + assign_hardware_id(); > + > + return 0; > +} > diff --git a/board/intel/edison/edison_start.S > b/board/intel/edison/edison_start.S This file should be renamed to just start.S > new file mode 100644 > index 0000000000..932fe6c24b > --- /dev/null > +++ b/board/intel/edison/edison_start.S > @@ -0,0 +1,13 @@ > +/* > + * Copyright (c) 2011 The Chromium OS Authors. > + * (C) Copyright 2008 > + * Graeme Russ, graeme.r...@gmail.com. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/* board early intialization */ > +.globl early_board_init > +early_board_init: > + /* No 32-bit board specific initialisation */ > + jmp early_board_init_ret > diff --git a/configs/edison_defconfig b/configs/edison_defconfig > new file mode 100644 > index 0000000000..f33b35c8d2 > --- /dev/null > +++ b/configs/edison_defconfig > @@ -0,0 +1,53 @@ > +CONFIG_X86=y > +CONFIG_VENDOR_INTEL=y > +CONFIG_DEFAULT_DEVICE_TREE="edison" > +CONFIG_TARGET_EDISON=y > +CONFIG_SMP=y > +# CONFIG_ARCH_EARLY_INIT_R is not set > +# CONFIG_BOARD_EARLY_INIT_F is not set > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_CPU=y > +# CONFIG_CMD_IMLS is not set > +CONFIG_CMD_ASKENV=y > +CONFIG_CMD_GREPENV=y > +CONFIG_CMD_ENV_CALLBACK=y > +CONFIG_CMD_ENV_FLAGS=y > +CONFIG_CMD_MEMINFO=y > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_DFU=y > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_TIMER=y > +CONFIG_CMD_HASH=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_EXT4_WRITE=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_FS_GENERIC=y > +CONFIG_OF_CONTROL=y > +CONFIG_OF_EMBED=y > +CONFIG_CPU=y > +CONFIG_DFU_MMC=y > +CONFIG_DFU_RAM=y > +CONFIG_MMC=y > +CONFIG_DM_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_SDMA=y > +CONFIG_MMC_SDHCI_TANGIER=y > +CONFIG_DM_PCI=y > +CONFIG_DM_PCI_COMPAT=y > +CONFIG_DM_RTC=y > +CONFIG_INTEL_MID_SERIAL=y > +CONFIG_TIMER=y > +CONFIG_USB_DWC3=y > +CONFIG_USB_DWC3_GADGET=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_DOWNLOAD=y > +CONFIG_G_DNL_MANUFACTURER="Intel" > +CONFIG_G_DNL_VENDOR_NUM=0x8087 > +CONFIG_G_DNL_PRODUCT_NUM=0x0a99 > +CONFIG_TANGIER_WATCHDOG=y > +CONFIG_FAT_WRITE=y > +CONFIG_USE_PRIVATE_LIBGCC=y > +CONFIG_SHA1=y > diff --git a/doc/README.x86 b/doc/README.x86 > index c69dc1c511..9eb541d0f8 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -18,6 +18,8 @@ U-Boot supports running as a coreboot [1] payload on x86. > So far only Link > work with minimal adjustments on other x86 boards since coreboot deals with > most of the low-level details. > > +U-boot is a main bootloader on Intel Edison board. U-Boot > + > U-Boot also supports booting directly from x86 reset vector, without > coreboot. > In this case, known as bare mode, from the fact that it runs on the > 'bare metal', U-Boot acts like a BIOS replacement. The following platforms > @@ -61,6 +63,16 @@ Change the 'Board configuration file' and 'Board Device > Tree Source (dts) file' > to point to a new board. You can also change the Cache-As-RAM (CAR) related > settings here if the default values do not fit your new board. > > +Build Instructions for U-Boot as main bootloader > +------------------------------------------------ > + > +Intel Edison instructions: > + > +Simple you can build U-Boot and obtain u-boot.bin > + > +$ make edison_defconfig > +$ make all > + > Build Instructions for U-Boot as BIOS replacement (bare mode) > ------------------------------------------------------------- > Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a > @@ -455,6 +467,33 @@ Here the kernel (bzImage) is loaded to 01000000 and > initrd is to 04000000. Then, > > => zboot 01000000 - 04000000 1b1ab50 > > +Updating U-Boot on Edison > +------------------------- > +By default Intel Edison boards are shipped with preinstalled heavily > +patched U-Boot v2014.04. Though it supports DFU which we may be able to > +use. > + > +1. Prepare u-boot.bin as described in chapter above. You still need one > +more step (if and only if you have original U-Boot), i.e. run the > +following command: > + > +$ truncate -s %4096 u-boot.bin > + > +2. Run your board and interrupt booting to U-Boot console. In the console > +call: > + > + => run do_force_flash_os > + > +3. Wait for few seconds, it will prepare environment variable and runs > +DFU. Run DFU command from the host system: > + > +$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin > + > +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and > +reset the board: > + > + => reset > + Are there instructions on how to program U-Boot on a board that does not have pre-flashed U-Boot? or in a situation that users flashed a bad image that makes the board brick. > CPU Microcode > ------------- > Modern CPUs usually require a special bit stream called microcode [8] to be > diff --git a/include/configs/edison.h b/include/configs/edison.h > new file mode 100644 > index 0000000000..8f28cba200 > --- /dev/null > +++ b/include/configs/edison.h > @@ -0,0 +1,78 @@ > +/* > + * Copyright (c) 2017 Intel Corp. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <asm/ibmpc.h> > + > +/*----------------------------------------------------------------------- nits: /* Boot */ > + * Boot > + */ > + > +#define CONFIG_CMD_ZBOOT > +#define CONFIG_BOOTCOMMAND "run bootcmd" > + > +/*----------------------------------------------------------------------- > + * DISK Partition support > + */ > + ditto > +#define CONFIG_RANDOM_UUID > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_SYS_CBSIZE 2048 > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + > sizeof(CONFIG_SYS_PROMPT) + 16) > +#define CONFIG_SYS_MAXARGS 128 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_AUTO_COMPLETE > + > +/*----------------------------------------------------------------------- > + * Memory > + */ > + > +#define CONFIG_SYS_LOAD_ADDR 0x100000 > +#define CONFIG_PHYSMEM > + > +#define CONFIG_NR_DRAM_BANKS 3 > + > +#define CONFIG_SYS_STACK_SIZE (32 * 1024) > + > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE > +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) > + > +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) > + > +#define CONFIG_SYS_MEMTEST_START 0x00100000 > +#define CONFIG_SYS_MEMTEST_END 0x01000000 > + > +/*----------------------------------------------------------------------- > + * Environment > + */ > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_SYS_MMC_ENV_DEV 0 > +#define CONFIG_SYS_MMC_ENV_PART 0 > +#define CONFIG_ENV_SIZE (64 * 1024) > +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) > +#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) > +#define CONFIG_SUPPORT_EMMC_BOOT > + > +/*----------------------------------------------------------------------- > + * PCI > + */ > + > +#define CONFIG_CMD_PCI > + > +/*----------------------------------------------------------------------- > + * RTC > + */ > + > +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 > +#define CONFIG_RTC_MC146818 > + > +#endif > -- Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot