Add a U-Boot specific dts file, which encapsulates the needed
modifications to the Gazerbeam Linux device tree.
Signed-off-by: Mario Six <mario....@gdsys.cc>
---
arch/powerpc/dts/gazerbeam.dts | 2 +
arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 192 ++++++++++++++++++++++++++++
2 files changed, 194 insertions(+)
create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts
index 35b7af4173..df0081e5c4 100644
--- a/arch/powerpc/dts/gazerbeam.dts
+++ b/arch/powerpc/dts/gazerbeam.dts
@@ -537,3 +537,5 @@
};
};
+
+/include/ "gdsys/gazerbeam-uboot.dtsi"
diff --git a/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
new file mode 100644
index 0000000000..37a5d78283
--- /dev/null
+++ b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi
@@ -0,0 +1,192 @@
+/ {
+ aliases {
+ i2c0 = &IIC;
+ i2c1 = &IIC2;
+ i2c2 = "/fpga0bus/fpga0_iic_main";
+ i2c3 = "/fpga0bus/fpga0_iic_video0";
+ i2c4 = "/fpga0bus/fpga0_iic_video1";
+ i2c5 = "/fpga0bus/fpga0_iic_usb";
+ };
+
+ REGMAP0: registermap {
+ compatible = "gdsys,ihs-fpga-regmap";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ reflection-low@0,15 {
+ compatible = "reflection-low";
+ reg = <0x0 15 16>;
+ };
+
+ versions@2,15 {
+ compatible = "versions";
+ reg = <0x2 15 16>;
+ };
+
+ fpga-version@4,15 {
+ compatible = "fpga-version";
+ reg = <0x4 15 16>;
+ };
+
+ fpga-features@6,15 {
+ compatible = "fpga-features";
+ reg = <0x6 15 16>;
+ };
+
+ fpga-ext-features@8,15 {
+ compatible = "fpga-ext-features";
+ reg = <0x8 15 16>;
+ };
+
+ control@10,15 {
+ compatible = "control";
+ reg = <0x2 15 16>;
+ };
+
+ top-interrupt@A,15 {
+ compatible = "top-interrupt";
+ reg = <0xA 15 16>;
+ };
+ };
+};
+
+&FPGA0 {
+ regmap = <®MAP0>;
+
+ reset-gpios = <&IOPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+ startupfin-gpios = <&gpio0 1 0 &gpio0 2 0>;
+};
+
+&FPGA0BUS {
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+
+ fpga0_rxaui@fc0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fc0 0x10>;
+ };
+
+ fpga0_rxaui@fd0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fd0 0x10>;
+ };
+
+ fpga0_rxaui@fe0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0fe0 0x10>;
+ };
+
+ fpga0_rxaui@ff0 {
+ compatible = "gdsys,rxaui_ctrl";
+ reg = <0x0ff0 0x10>;
+ };
+
+ fpga0_video0 {
+ mode = "640_480_60";
+ };
+
+ fpga0_axi_video0 {
+ fpga0_dp_video0 {
+ clocks = <&fpga0_video0_clkgen>;
+ };
+ };
+
+ fpga0_iic_video0 {
+ fpga0_video0_clkgen {
+ #clock-cells = <0>;
+ };
+ };
+
+ fpga0_video1 {
+ mode = "640_480_60";
+ };
+
+ fpga0_axi_video1 {
+ fpga0_dp_video1 {
+ clocks = <&fpga0_video0_clkgen>;
+ };
+ };
+
+ fpga0_iic_video1 {
+ fpga0_video1_clkgen {
+ #clock-cells = <0>;
+ };
+ };
+};
+
+&FPGA1BUS {
+ fpga1_video0 {
+ mode = "640_480_60";
+ };
+
+ fpga1_axi_video0 {
+ fpga1_dp_video0 {
+ clocks = <&fpga0_video0_clkgen>;
+ };
+ };
+
+ fpga1_iic_video0 {
+ fpga1_video0_clkgen {
+ #clock-cells = <0>;
+ };
+ };
+
+ fpga1_video1 {
+ mode = "640_480_60";
+ };
+
+ fpga1_axi_video1 {
+ fpga1_dp_video1 {
+ clocks = <&fpga0_video0_clkgen>;
+ };
+ };
+
+ fpga1_iic_video1 {
+ fpga1_video1_clkgen {
+ #clock-cells = <0>;
+ };
+ };
+};
+
+&board_soc {
+ u-boot,dm-pre-reloc;
+};
+
+&IIC {
+ compatible = "fsl-i2c";
+ u-boot,dm-pre-reloc;
+
+ IOPCA: pca9698@20 {
+ u-boot,dm-pre-reloc;
+ };
+
+ PPCPCA: pca9698@22 {
+ u-boot,dm-pre-reloc;
+ };
+
+ at97sc3205t@29 {
+ u-boot,i2c-offset-len = <0>;
+ };
+};
+
+&IIC2 {
+ compatible = "fsl-i2c";
+ u-boot,dm-pre-reloc;
+
+ GPIO_VB0: pca9698@20 {
+ u-boot,dm-pre-reloc;
+ };
+
+ GPIO_VB1: pca9698@22 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&GPIO_VB0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio0 {
+ ngpios = <24>;
+};
--
2.11.0
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