USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v5:
Use scfg_clrsetbits32() instead.
Change in v4:
Change 1001 to 0x9 in the commit message to match the code.
Clean up the math in set_usb_txvreftune().
Rename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.
Change in v3:
Use inline function to make code cleaner.
Change in v2:
In function erratum_a009008():
1.Put a blank line after variable declaration.
2.Move common code together.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 37 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cdeef26fe5..d8936a4334 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -22,6 +22,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -44,6 +45,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -80,6 +82,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
+ select SYS_FSL_ERRATUM_A009008
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -223,6 +226,10 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 639e9d2ddc..ea71fa0dc7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,27 @@ bool soc_has_aiop(void)
return false;
}
+static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrsetbits32(scfg + offset / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+}
+
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+ set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -198,6 +219,7 @@ void fsl_lsch3_early_init_f(void)
#endif
erratum_a008514();
erratum_a008336();
+ erratum_a009008();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -473,6 +495,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+ erratum_a009008();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 4afc338b8e..c60d8ddfa2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -338,6 +338,12 @@ struct ccsr_gur {
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB_TXVREFTUNE 0x9
+
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 59410aa7e7..01b24d03f1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -133,6 +133,7 @@
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
+#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
2.14.1
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