USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v4:
Use clrsetbits_be32() instead.
Change in v4:
Change 1001 to 0x9 in the commit message to match the code.
Clean up the math in register setting.
Rename USB_TXVREFTUNE TO SCFG_USB_TXVREFTUNE.
Change in v3:
- none
Change in v2:
In function erratum_a009008():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++
arch/arm/cpu/armv7/ls102xa/soc.c | 15 +++++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++
3 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index fadfce4f05..599cc28249 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -52,6 +53,11 @@ config SECURE_BOOT
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
+ bool
+ help
+ Workaround for USB erratum A009008
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b84a1a686a..1c59a62a0e 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void)
return major;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
void s_init(void)
{
}
@@ -146,6 +158,9 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */
+ erratum_a009008();
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63e66..ba59f40382 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR 0x070
+#define SCFG_USB_TXVREFTUNE 0x9
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
--
2.14.1
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