The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <sba...@denx.de>
---
cpu/arm_cortexa8/mx51/lowlevel_init.S | 5 ++++-
include/configs/mx51evk.h | 3 +++
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/cpu/arm_cortexa8/mx51/lowlevel_init.S
b/cpu/arm_cortexa8/mx51/lowlevel_init.S
index 31af9e2..1e393bb 100644
--- a/cpu/arm_cortexa8/mx51/lowlevel_init.S
+++ b/cpu/arm_cortexa8/mx51/lowlevel_init.S
@@ -158,6 +158,7 @@
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
@@ -171,6 +172,7 @@
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
mov r3, #DP_OP_216
@@ -201,9 +203,10 @@
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =0x59E35100
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index e2daeca..5096ab7 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -177,6 +177,9 @@
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
--
1.6.3.3
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