Change the size create a glitch in the clke signal on second
bank. The glitch can generate problem in memory initialiazation
Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com>
---
arch/arm/mach-sunxi/dram_sun8i_a33.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c
b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index 83212aaddf..d73a93a132 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -45,14 +45,12 @@ static void mctl_set_cr(struct dram_para *para)
static void auto_detect_dram_size(struct dram_para *para)
{
- u8 orig_rank = para->rank;
int rows, columns;
/* Row detect */
para->page_size = 512;
para->seq = 1;
para->rows = 16;
- para->rank = 1;
mctl_set_cr(para);
for (rows = 11 ; rows < 16 ; rows++) {
if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
@@ -69,7 +67,6 @@ static void auto_detect_dram_size(struct dram_para *para)
}
para->seq = 0;
- para->rank = orig_rank;
para->rows = rows;
para->page_size = 1 << columns;
mctl_set_cr(para);
--
2.17.1
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