> -----Original Message----- > From: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > Sent: Wednesday, March 6, 2019 4:23 AM > To: u-boot@lists.denx.de > Cc: Atish Patra <atish.pa...@wdc.com>; Anup Patel > <anup.pa...@wdc.com>; Bin Meng <bmeng...@gmail.com>; Andreas > Schwab <sch...@suse.de>; Palmer Dabbelt <pal...@sifive.com>; > Alexander Graf <ag...@suse.de>; Lukas Auer > <lukas.a...@aisec.fraunhofer.de>; Anup Patel <anup.pa...@wdc.com>; > Anup Patel <a...@brainfault.org>; Rick Chen <r...@andestech.com>; > Baruch Siach <bar...@tkos.co.il>; Atish Patra <atish.pa...@wdc.com>; > Stefan Roese <s...@denx.de>; Paul Walmsley <paul.walms...@sifive.com>; > Daniel Schwierzeck <daniel.schwierz...@gmail.com> > Subject: [PATCH v2 0/9] SMP support for RISC-V > > This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to > run on multi-hart systems (hart is the RISC-V terminology for hardware > thread). Images passed to bootm will be started on all harts. > The bootm command is currently the only one that will boot images on all > harts, bootefi is not yet supported. > > The patches have been successfully tested on both QEMU (machine and > supervisor mode) and the HiFive Unleashed board (supervisor mode), using > BBL and OpenSBI. > Mainline QEMU requires two patches [1, 2] to run in this configuration. > > [1]: https://patchwork.ozlabs.org/patch/1039493/ > [2]: https://patchwork.ozlabs.org/patch/1039082/ > > Changes in v2: > - Remove unneeded quotes from NR_CPUS Kconfig entry > - Move memory barrier from send_ipi_many() to handle_ipi() > - Add check in send_ipi_many so that IPIs are only sent to available harts as > indicated by the available_harts mask > - Implement hart lottery to pick main hart to run U-Boot > - Remove CONFIG_MAIN_HART as it is not required anymore > - Register available harts in the available_harts mask > - New patch to populate register a0 with the hart ID from the mhartid CSR in > machine-mode > - New patch to enable SMP on the SiFive FU540, which was previously sent > independently > > Lukas Auer (9): > riscv: add infrastructure for calling functions on other harts > riscv: import the supervisor binary interface header file > riscv: implement IPI platform functions using SBI > riscv: delay initialization of caches and debug UART > riscv: add support for multi-hart systems > riscv: boot images passed to bootm on all harts > riscv: do not rely on hart ID passed by previous boot stage > riscv: fu540: enable SMP > riscv: qemu: enable SMP > > arch/riscv/Kconfig | 28 +++++ > arch/riscv/cpu/cpu.c | 9 +- > arch/riscv/cpu/start.S | 152 +++++++++++++++++++++++++-- > arch/riscv/include/asm/csr.h | 1 + > arch/riscv/include/asm/global_data.h | 6 ++ > arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ > arch/riscv/include/asm/smp.h | 53 ++++++++++ > arch/riscv/lib/Makefile | 2 + > arch/riscv/lib/asm-offsets.c | 1 + > arch/riscv/lib/bootm.c | 13 ++- > arch/riscv/lib/sbi_ipi.c | 25 +++++ > arch/riscv/lib/smp.c | 116 ++++++++++++++++++++ > board/emulation/qemu-riscv/Kconfig | 1 + > board/sifive/fu540/Kconfig | 1 + > 14 files changed, 492 insertions(+), 10 deletions(-) create mode 100644 > arch/riscv/include/asm/sbi.h create mode 100644 > arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c > create mode 100644 arch/riscv/lib/smp.c > > -- > 2.20.1
I tried this series on U-Boot-2019.04-rc3 and works fine on SiFive Unleashed board. Tested-by: Anup Patel <anup.pa...@wdc.com> I have also pushed these patches to riscv_sifive_fu540_smp_v4 branch of https://github.com/avpatel/u-boot.git Regards, Anup _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
