Hi Marek, > Synchronize iMX53 device tree from Linux next-20190607 3f310e51ceb1 , > this is needed to get NFC, UART, USBOTG DT nodes. >
As fair as I remember, for the imx53 we only added the necessary nodes for imx53.dtsi Linux file as adding full DM/DTS caused some issues with the u-boot binary size (as it is not using SPL, but single binary). However, I'm not sure if this is still the case. > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Fabio Estevam <fabio.este...@nxp.com> > Cc: Stefano Babic <sba...@denx.de> > --- > arch/arm/dts/imx53.dtsi | 745 > +++++++++++++++++++++++++++++++--------- 1 file changed, 588 > insertions(+), 157 deletions(-) > > diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi > index 211ff5f69e..ed341cfd9d 100644 > --- a/arch/arm/dts/imx53.dtsi > +++ b/arch/arm/dts/imx53.dtsi > @@ -1,17 +1,8 @@ > -/* > - * Copyright 2016 Beckhoff Automation > - * Copyright 2011 Freescale Semiconductor, Inc. > - * Copyright 2011 Linaro Ltd. > - * > - * The code contained herein is licensed under the GNU General Public > - * License. You may obtain a copy of the GNU General Public License > - * Version 2 or later at the following locations: > - * > - * http://www.opensource.org/licenses/gpl-license.html > - * http://www.gnu.org/copyleft/gpl.html > - */ > - > -#include "skeleton.dtsi" > +// SPDX-License-Identifier: GPL-2.0+ > +// > +// Copyright 2011 Freescale Semiconductor, Inc. > +// Copyright 2011 Linaro Ltd. > + > #include "imx53-pinfunc.h" > #include <dt-bindings/clock/imx5-clock.h> > #include <dt-bindings/gpio/gpio.h> > @@ -19,8 +10,17 @@ > #include <dt-bindings/interrupt-controller/irq.h> > > / { > + #address-cells = <1>; > + #size-cells = <1>; > + /* > + * The decompressor and also some bootloaders rely on a > + * pre-existing /chosen node to be available to insert the > + * command line and merge other ATAGS info. > + */ > + chosen {}; > + > aliases { > - serial1 = &uart2; > + ethernet0 = &fec; > gpio0 = &gpio1; > gpio1 = &gpio2; > gpio2 = &gpio3; > @@ -36,7 +36,45 @@ > mmc1 = &esdhc2; > mmc2 = &esdhc3; > mmc3 = &esdhc4; > - usb1 = &usbh1; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > + spi0 = &ecspi1; > + spi1 = &ecspi2; > + spi2 = &cspi; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a8"; > + reg = <0x0>; > + clocks = <&clks IMX5_CLK_ARM>; > + clock-latency = <61036>; > + voltage-tolerance = <5>; > + operating-points = < > + /* kHz */ > + 166666 850000 > + 400000 900000 > + 800000 1050000 > + 1000000 1200000 > + 1200000 1300000 > + >; > + }; > + }; > + > + display-subsystem { > + compatible = "fsl,imx-display-subsystem"; > + ports = <&ipu_di0>, <&ipu_di1>; > + }; > + > + capture_subsystem { > + compatible = "fsl,imx-capture-subsystem"; > + ports = <&ipu_csi0>, <&ipu_csi1>; > }; > > tzic: tz-interrupt-controller@fffc000 { > @@ -46,13 +84,143 @@ > reg = <0x0fffc000 0x4000>; > }; > > + clocks { > + ckil { > + compatible = "fsl,imx-ckil", "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > + > + ckih1 { > + compatible = "fsl,imx-ckih1", "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <22579200>; > + }; > + > + ckih2 { > + compatible = "fsl,imx-ckih2", "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + }; > + > + osc { > + compatible = "fsl,imx-osc", "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + }; > + > + pmu: pmu { > + compatible = "arm,cortex-a8-pmu"; > + interrupt-parent = <&tzic>; > + interrupts = <77>; > + }; > + > + usbphy0: usbphy-0 { > + compatible = "usb-nop-xceiv"; > + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; > + clock-names = "main_clk"; > + #phy-cells = <0>; > + status = "okay"; > + }; > + > + usbphy1: usbphy-1 { > + compatible = "usb-nop-xceiv"; > + clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; > + clock-names = "main_clk"; > + #phy-cells = <0>; > + status = "okay"; > + }; > + > soc { > #address-cells = <1>; > #size-cells = <1>; > compatible = "simple-bus"; > interrupt-parent = <&tzic>; > ranges; > - u-boot,dm-pre-reloc; > + > + sata: sata@10000000 { > + compatible = "fsl,imx53-ahci"; > + reg = <0x10000000 0x1000>; > + interrupts = <28>; > + clocks = <&clks IMX5_CLK_SATA_GATE>, > + <&clks IMX5_CLK_SATA_REF>, > + <&clks IMX5_CLK_AHB>; > + clock-names = "sata", "sata_ref", "ahb"; > + status = "disabled"; > + }; > + > + ipu: ipu@18000000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx53-ipu"; > + reg = <0x18000000 0x08000000>; > + interrupts = <11 10>; > + clocks = <&clks IMX5_CLK_IPU_GATE>, > + <&clks IMX5_CLK_IPU_DI0_GATE>, > + <&clks IMX5_CLK_IPU_DI1_GATE>; > + clock-names = "bus", "di0", "di1"; > + resets = <&src 2>; > + > + ipu_csi0: port@0 { > + reg = <0>; > + > + ipu_csi0_from_parallel_sensor: > endpoint { > + }; > + }; > + > + ipu_csi1: port@1 { > + reg = <1>; > + > + ipu_csi1_from_parallel_sensor: > endpoint { > + }; > + }; > + > + ipu_di0: port@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <2>; > + > + ipu_di0_disp0: endpoint@0 { > + reg = <0>; > + }; > + > + ipu_di0_lvds0: endpoint@1 { > + reg = <1>; > + remote-endpoint = > <&lvds0_in>; > + }; > + }; > + > + ipu_di1: port@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <3>; > + > + ipu_di1_disp1: endpoint@0 { > + reg = <0>; > + }; > + > + ipu_di1_lvds1: endpoint@1 { > + reg = <1>; > + remote-endpoint = > <&lvds1_in>; > + }; > + > + ipu_di1_tve: endpoint@2 { > + reg = <2>; > + remote-endpoint = <&tve_in>; > + }; > + }; > + }; > + > + gpu: gpu@30000000 { > + compatible = "amd,imageon-200.0", > "amd,imageon"; > + reg = <0x30000000 0x20000>; > + reg-names = "kgsl_3d0_reg_memory"; > + interrupts = <12>; > + interrupt-names = "kgsl_3d0_irq"; > + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks > IMX5_CLK_GARB_GATE>; > + clock-names = "core_clk", "mem_iface_clk"; > + }; > > aips@50000000 { /* AIPS1 */ > compatible = "fsl,aips-bus", "simple-bus"; > @@ -92,6 +260,47 @@ > status = "disabled"; > }; > > + uart3: serial@5000c000 { > + compatible = > "fsl,imx53-uart", "fsl,imx21-uart"; > + reg = <0x5000c000 0x4000>; > + interrupts = <33>; > + clocks = <&clks > IMX5_CLK_UART3_IPG_GATE>, > + <&clks > IMX5_CLK_UART3_PER_GATE>; > + clock-names = "ipg", "per"; > + dmas = <&sdma 42 4 0>, > <&sdma 43 4 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + ecspi1: spi@50010000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = > "fsl,imx53-ecspi", "fsl,imx51-ecspi"; > + reg = <0x50010000 0x4000>; > + interrupts = <36>; > + clocks = <&clks > IMX5_CLK_ECSPI1_IPG_GATE>, > + <&clks > IMX5_CLK_ECSPI1_PER_GATE>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ssi2: ssi@50014000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx53-ssi", > + "fsl,imx51-ssi", > + "fsl,imx21-ssi"; > + reg = <0x50014000 0x4000>; > + interrupts = <30>; > + clocks = <&clks > IMX5_CLK_SSI2_IPG_GATE>, > + <&clks > IMX5_CLK_SSI2_ROOT_GATE>; > + clock-names = "ipg", "baud"; > + dmas = <&sdma 24 1 0>, > + <&sdma 25 1 0>; > + dma-names = "rx", "tx"; > + fsl,fifo-depth = <15>; > + status = "disabled"; > + }; > + > esdhc3: esdhc@50020000 { > compatible = > "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; > @@ -117,25 +326,18 @@ > }; > }; > > - iomuxc: iomuxc@53fa8000 { > - compatible = "fsl,imx53-iomuxc"; > - reg = <0x53fa8000 0x4000>; > - }; > - > - gpr: iomuxc-gpr@53fa8000 { > - compatible = "fsl,imx53-iomuxc-gpr", > "syscon"; > - reg = <0x53fa8000 0xc>; > + aipstz1: bridge@53f00000 { > + compatible = "fsl,imx53-aipstz"; > + reg = <0x53f00000 0x60>; > }; > > - uart2: serial@53fc0000 { > - compatible = "fsl,imx7d-uart", > "fsl,imx53-uart", "fsl,imx21-uart"; > - reg = <0x53fc0000 0x4000>; > - interrupts = <32>; > - clocks = <&clks > IMX5_CLK_UART2_IPG_GATE>, > - <&clks > IMX5_CLK_UART2_PER_GATE>; > - clock-names = "ipg", "per"; > - dmas = <&sdma 12 4 0>, <&sdma 13 4 > 0>; > - dma-names = "rx", "tx"; > + usbotg: usb@53f80000 { > + compatible = "fsl,imx53-usb", > "fsl,imx27-usb"; > + reg = <0x53f80000 0x0200>; > + interrupts = <18>; > + clocks = <&clks > IMX5_CLK_USBOH3_GATE>; > + fsl,usbmisc = <&usbmisc 0>; > + fsl,usbphy = <&usbphy0>; > status = "disabled"; > }; > > @@ -144,15 +346,37 @@ > reg = <0x53f80200 0x0200>; > interrupts = <14>; > clocks = <&clks > IMX5_CLK_USBOH3_GATE>; > + fsl,usbmisc = <&usbmisc 1>; > + fsl,usbphy = <&usbphy1>; > dr_mode = "host"; > status = "disabled"; > }; > > - clks: ccm@53fd4000{ > - compatible = "fsl,imx53-ccm"; > - reg = <0x53fd4000 0x4000>; > - interrupts = <0 71 0x04 0 72 0x04>; > - #clock-cells = <1>; > + usbh2: usb@53f80400 { > + compatible = "fsl,imx53-usb", > "fsl,imx27-usb"; > + reg = <0x53f80400 0x0200>; > + interrupts = <16>; > + clocks = <&clks > IMX5_CLK_USBOH3_GATE>; > + fsl,usbmisc = <&usbmisc 2>; > + dr_mode = "host"; > + status = "disabled"; > + }; > + > + usbh3: usb@53f80600 { > + compatible = "fsl,imx53-usb", > "fsl,imx27-usb"; > + reg = <0x53f80600 0x0200>; > + interrupts = <17>; > + clocks = <&clks > IMX5_CLK_USBOH3_GATE>; > + fsl,usbmisc = <&usbmisc 3>; > + dr_mode = "host"; > + status = "disabled"; > + }; > + > + usbmisc: usbmisc@53f80800 { > + #index-cells = <1>; > + compatible = "fsl,imx53-usbmisc"; > + reg = <0x53f80800 0x200>; > + clocks = <&clks > IMX5_CLK_USBOH3_GATE>; }; > > gpio1: gpio@53f84000 { > @@ -195,6 +419,188 @@ > #interrupt-cells = <2>; > }; > > + kpp: kpp@53f94000 { > + compatible = "fsl,imx53-kpp", > "fsl,imx21-kpp"; > + reg = <0x53f94000 0x4000>; > + interrupts = <60>; > + clocks = <&clks IMX5_CLK_DUMMY>; > + status = "disabled"; > + }; > + > + wdog1: wdog@53f98000 { > + compatible = "fsl,imx53-wdt", > "fsl,imx21-wdt"; > + reg = <0x53f98000 0x4000>; > + interrupts = <58>; > + clocks = <&clks IMX5_CLK_DUMMY>; > + }; > + > + wdog2: wdog@53f9c000 { > + compatible = "fsl,imx53-wdt", > "fsl,imx21-wdt"; > + reg = <0x53f9c000 0x4000>; > + interrupts = <59>; > + clocks = <&clks IMX5_CLK_DUMMY>; > + status = "disabled"; > + }; > + > + gpt: timer@53fa0000 { > + compatible = "fsl,imx53-gpt", > "fsl,imx31-gpt"; > + reg = <0x53fa0000 0x4000>; > + interrupts = <39>; > + clocks = <&clks > IMX5_CLK_GPT_IPG_GATE>, > + <&clks > IMX5_CLK_GPT_HF_GATE>; > + clock-names = "ipg", "per"; > + }; > + > + srtc: rtc@53fa4000 { > + compatible = "fsl,imx53-rtc"; > + reg = <0x53fa4000 0x4000>; > + interrupts = <24>; > + clocks = <&clks IMX5_CLK_SRTC_GATE>; > + }; > + > + iomuxc: iomuxc@53fa8000 { > + compatible = "fsl,imx53-iomuxc"; > + reg = <0x53fa8000 0x4000>; > + }; > + > + gpr: iomuxc-gpr@53fa8000 { > + compatible = "fsl,imx53-iomuxc-gpr", > "syscon"; > + reg = <0x53fa8000 0xc>; > + }; > + > + ldb: ldb@53fa8008 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx53-ldb"; > + reg = <0x53fa8008 0x4>; > + gpr = <&gpr>; > + clocks = <&clks > IMX5_CLK_LDB_DI0_SEL>, > + <&clks > IMX5_CLK_LDB_DI1_SEL>, > + <&clks > IMX5_CLK_IPU_DI0_SEL>, > + <&clks > IMX5_CLK_IPU_DI1_SEL>, > + <&clks > IMX5_CLK_LDB_DI0_GATE>, > + <&clks > IMX5_CLK_LDB_DI1_GATE>; > + clock-names = "di0_pll", "di1_pll", > + "di0_sel", "di1_sel", > + "di0", "di1"; > + status = "disabled"; > + > + lvds-channel@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + status = "disabled"; > + > + port@0 { > + reg = <0>; > + > + lvds0_in: endpoint { > + > remote-endpoint = <&ipu_di0_lvds0>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + }; > + }; > + > + lvds-channel@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + status = "disabled"; > + > + port@1 { > + reg = <1>; > + > + lvds1_in: endpoint { > + > remote-endpoint = <&ipu_di1_lvds1>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + }; > + }; > + }; > + > + pwm1: pwm@53fb4000 { > + #pwm-cells = <2>; > + compatible = "fsl,imx53-pwm", > "fsl,imx27-pwm"; > + reg = <0x53fb4000 0x4000>; > + clocks = <&clks > IMX5_CLK_PWM1_IPG_GATE>, > + <&clks > IMX5_CLK_PWM1_HF_GATE>; > + clock-names = "ipg", "per"; > + interrupts = <61>; > + }; > + > + pwm2: pwm@53fb8000 { > + #pwm-cells = <2>; > + compatible = "fsl,imx53-pwm", > "fsl,imx27-pwm"; > + reg = <0x53fb8000 0x4000>; > + clocks = <&clks > IMX5_CLK_PWM2_IPG_GATE>, > + <&clks > IMX5_CLK_PWM2_HF_GATE>; > + clock-names = "ipg", "per"; > + interrupts = <94>; > + }; > + > + uart1: serial@53fbc000 { > + compatible = "fsl,imx53-uart", > "fsl,imx21-uart"; > + reg = <0x53fbc000 0x4000>; > + interrupts = <31>; > + clocks = <&clks > IMX5_CLK_UART1_IPG_GATE>, > + <&clks > IMX5_CLK_UART1_PER_GATE>; > + clock-names = "ipg", "per"; > + dmas = <&sdma 18 4 0>, <&sdma 19 4 > 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + uart2: serial@53fc0000 { > + compatible = "fsl,imx53-uart", > "fsl,imx21-uart"; > + reg = <0x53fc0000 0x4000>; > + interrupts = <32>; > + clocks = <&clks > IMX5_CLK_UART2_IPG_GATE>, > + <&clks > IMX5_CLK_UART2_PER_GATE>; > + clock-names = "ipg", "per"; > + dmas = <&sdma 12 4 0>, <&sdma 13 4 > 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + can1: can@53fc8000 { > + compatible = "fsl,imx53-flexcan", > "fsl,imx25-flexcan"; > + reg = <0x53fc8000 0x4000>; > + interrupts = <82>; > + clocks = <&clks > IMX5_CLK_CAN1_IPG_GATE>, > + <&clks > IMX5_CLK_CAN1_SERIAL_GATE>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + can2: can@53fcc000 { > + compatible = "fsl,imx53-flexcan", > "fsl,imx25-flexcan"; > + reg = <0x53fcc000 0x4000>; > + interrupts = <83>; > + clocks = <&clks > IMX5_CLK_CAN2_IPG_GATE>, > + <&clks > IMX5_CLK_CAN2_SERIAL_GATE>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + src: src@53fd0000 { > + compatible = "fsl,imx53-src", > "fsl,imx51-src"; > + reg = <0x53fd0000 0x4000>; > + #reset-cells = <1>; > + }; > + > + clks: ccm@53fd4000{ > + compatible = "fsl,imx53-ccm"; > + reg = <0x53fd4000 0x4000>; > + interrupts = <0 71 0x04 0 72 0x04>; > + #clock-cells = <1>; > + }; > + > gpio5: gpio@53fdc000 { > compatible = "fsl,imx53-gpio", > "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; > @@ -234,6 +640,18 @@ > clocks = <&clks IMX5_CLK_I2C3_GATE>; > status = "disabled"; > }; > + > + uart4: serial@53ff0000 { > + compatible = "fsl,imx53-uart", > "fsl,imx21-uart"; > + reg = <0x53ff0000 0x4000>; > + interrupts = <13>; > + clocks = <&clks > IMX5_CLK_UART4_IPG_GATE>, > + <&clks > IMX5_CLK_UART4_PER_GATE>; > + clock-names = "ipg", "per"; > + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > }; > > aips@60000000 { /* AIPS2 */ > @@ -243,25 +661,74 @@ > reg = <0x60000000 0x10000000>; > ranges; > > + aipstz2: bridge@63f00000 { > + compatible = "fsl,imx53-aipstz"; > + reg = <0x63f00000 0x60>; > + }; > + > + iim: iim@63f98000 { > + compatible = "fsl,imx53-iim", > "fsl,imx27-iim"; > + reg = <0x63f98000 0x4000>; > + interrupts = <69>; > + clocks = <&clks IMX5_CLK_IIM_GATE>; > + }; > + > + uart5: serial@63f90000 { > + compatible = "fsl,imx53-uart", > "fsl,imx21-uart"; > + reg = <0x63f90000 0x4000>; > + interrupts = <86>; > + clocks = <&clks > IMX5_CLK_UART5_IPG_GATE>, > + <&clks > IMX5_CLK_UART5_PER_GATE>; > + clock-names = "ipg", "per"; > + dmas = <&sdma 16 4 0>, <&sdma 17 4 > 0>; > + dma-names = "rx", "tx"; > + status = "disabled"; > + }; > + > + tigerp: tigerp@63fa0000 { > + compatible = "fsl,imx53-tigerp", > "fsl,imx51-tigerp"; > + reg = <0x63fa0000 0x28>; > + }; > + > + owire: owire@63fa4000 { > + compatible = "fsl,imx53-owire", > "fsl,imx21-owire"; > + reg = <0x63fa4000 0x4000>; > + clocks = <&clks IMX5_CLK_OWIRE_GATE>; > + status = "disabled"; > + }; > + > + ecspi2: spi@63fac000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx53-ecspi", > "fsl,imx51-ecspi"; > + reg = <0x63fac000 0x4000>; > + interrupts = <37>; > + clocks = <&clks > IMX5_CLK_ECSPI2_IPG_GATE>, > + <&clks > IMX5_CLK_ECSPI2_PER_GATE>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > sdma: sdma@63fb0000 { > compatible = "fsl,imx53-sdma", > "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; > interrupts = <6>; > clocks = <&clks IMX5_CLK_SDMA_GATE>, > - <&clks IMX5_CLK_SDMA_GATE>; > + <&clks IMX5_CLK_AHB>; > clock-names = "ipg", "ahb"; > #dma-cells = <3>; > fsl,sdma-ram-script-name = > "imx/sdma/sdma-imx53.bin"; }; > > - fec: ethernet@63fec000 { > - compatible = "fsl,imx53-fec", > "fsl,imx25-fec"; > - reg = <0x63fec000 0x4000>; > - interrupts = <87>; > - clocks = <&clks IMX5_CLK_FEC_GATE>, > - <&clks IMX5_CLK_FEC_GATE>, > - <&clks IMX5_CLK_FEC_GATE>; > - clock-names = "ipg", "ahb", "ptp"; > + cspi: spi@63fc0000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx53-cspi", > "fsl,imx35-cspi"; > + reg = <0x63fc0000 0x4000>; > + interrupts = <38>; > + clocks = <&clks > IMX5_CLK_CSPI_IPG_GATE>, > + <&clks > IMX5_CLK_CSPI_IPG_GATE>; > + clock-names = "ipg", "per"; > status = "disabled"; > }; > > @@ -284,66 +751,65 @@ > clocks = <&clks IMX5_CLK_I2C1_GATE>; > status = "disabled"; > }; > - }; > - > - ipu: ipu@18000000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx53-ipu"; > - reg = <0x18000000 0x08000000>; > - interrupts = <11 10>; > - clocks = <&clks IMX5_CLK_IPU_GATE>, > - <&clks IMX5_CLK_IPU_DI0_GATE>, > - <&clks IMX5_CLK_IPU_DI1_GATE>; > - clock-names = "bus", "di0", "di1"; > - resets = <&src 2>; > - u-boot,dm-pre-reloc; > > - ipu_csi0: port@0 { > - reg = <0>; > + ssi1: ssi@63fcc000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx53-ssi", > "fsl,imx51-ssi", > + "fsl,imx21-ssi"; > + reg = <0x63fcc000 0x4000>; > + interrupts = <29>; > + clocks = <&clks > IMX5_CLK_SSI1_IPG_GATE>, > + <&clks > IMX5_CLK_SSI1_ROOT_GATE>; > + clock-names = "ipg", "baud"; > + dmas = <&sdma 28 0 0>, > + <&sdma 29 0 0>; > + dma-names = "rx", "tx"; > + fsl,fifo-depth = <15>; > + status = "disabled"; > }; > > - ipu_csi1: port@1 { > - reg = <1>; > + audmux: audmux@63fd0000 { > + compatible = "fsl,imx53-audmux", > "fsl,imx31-audmux"; > + reg = <0x63fd0000 0x4000>; > + status = "disabled"; > }; > > - ipu_di0: port@2 { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <2>; > - > - ipu_di0_disp0: endpoint@0 { > - reg = <0>; > - }; > - > - ipu_di0_lvds0: endpoint@1 { > - reg = <1>; > - remote-endpoint = > <&lvds0_in>; > - }; > + nfc: nand@63fdb000 { > + compatible = "fsl,imx53-nand"; > + reg = <0x63fdb000 0x1000 0xf7ff0000 > 0x10000>; > + interrupts = <8>; > + clocks = <&clks IMX5_CLK_NFC_GATE>; > + status = "disabled"; > }; > > - ipu_di1: port@3 { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <3>; > - > - ipu_di1_disp1: endpoint@0 { > - reg = <0>; > - }; > - > - ipu_di1_lvds1: endpoint@1 { > - reg = <1>; > - remote-endpoint = > <&lvds1_in>; > - }; > + ssi3: ssi@63fe8000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx53-ssi", > "fsl,imx51-ssi", > + "fsl,imx21-ssi"; > + reg = <0x63fe8000 0x4000>; > + interrupts = <96>; > + clocks = <&clks > IMX5_CLK_SSI3_IPG_GATE>, > + <&clks > IMX5_CLK_SSI3_ROOT_GATE>; > + clock-names = "ipg", "baud"; > + dmas = <&sdma 46 0 0>, > + <&sdma 47 0 0>; > + dma-names = "rx", "tx"; > + fsl,fifo-depth = <15>; > + status = "disabled"; > + }; > > - ipu_di1_tve: endpoint@2 { > - reg = <2>; > - remote-endpoint = <&tve_in>; > - }; > + fec: ethernet@63fec000 { > + compatible = "fsl,imx53-fec", > "fsl,imx25-fec"; > + reg = <0x63fec000 0x4000>; > + interrupts = <87>; > + clocks = <&clks IMX5_CLK_FEC_GATE>, > + <&clks IMX5_CLK_FEC_GATE>, > + <&clks IMX5_CLK_FEC_GATE>; > + clock-names = "ipg", "ahb", "ptp"; > + status = "disabled"; > }; > - }; > > - tve: tve@63ff0000 { > + tve: tve@63ff0000 { > compatible = "fsl,imx53-tve"; > reg = <0x63ff0000 0x1000>; > interrupts = <92>; > @@ -357,68 +823,33 @@ > remote-endpoint = > <&ipu_di1_tve>; }; > }; > - }; > - > - src: src@53fd0000 { > - compatible = "fsl,imx53-src", > "fsl,imx51-src"; > - reg = <0x53fd0000 0x4000>; > - #reset-cells = <1>; > - }; > - > - ldb: ldb@53fa8008 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx53-ldb"; > - reg = <0x53fa8008 0x4>; > - gpr = <&gpr>; > - clocks = <&clks > IMX5_CLK_LDB_DI0_SEL>, > - <&clks > IMX5_CLK_LDB_DI1_SEL>, > - <&clks > IMX5_CLK_IPU_DI0_SEL>, > - <&clks > IMX5_CLK_IPU_DI1_SEL>, > - <&clks > IMX5_CLK_LDB_DI0_GATE>, > - <&clks > IMX5_CLK_LDB_DI1_GATE>; > - clock-names = "di0_pll", "di1_pll", > - "di0_sel", "di1_sel", > - "di0", "di1"; > - status = "disabled"; > - > - lvds-channel@0 { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <0>; > - status = "disabled"; > - > - port@0 { > - reg = <0>; > - > - lvds0_in: endpoint { > - > remote-endpoint = <&ipu_di0_lvds0>; > - }; > - }; > - > - port@2 { > - reg = <2>; > - }; > - }; > - > - lvds-channel@1 { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <1>; > - status = "disabled"; > + }; > > - port@1 { > - reg = <1>; > + vpu: vpu@63ff4000 { > + compatible = "fsl,imx53-vpu", > "cnm,coda7541"; > + reg = <0x63ff4000 0x1000>; > + interrupts = <9>; > + clocks = <&clks > IMX5_CLK_VPU_REFERENCE_GATE>, > + <&clks IMX5_CLK_VPU_GATE>; > + clock-names = "per", "ahb"; > + resets = <&src 1>; > + iram = <&ocram>; > + }; > > - lvds1_in: endpoint { > - > remote-endpoint = <&ipu_di1_lvds1>; > - }; > - }; > + sahara: crypto@63ff8000 { > + compatible = "fsl,imx53-sahara"; > + reg = <0x63ff8000 0x4000>; > + interrupts = <19 20>; > + clocks = <&clks > IMX5_CLK_SAHARA_IPG_GATE>, > + <&clks > IMX5_CLK_SAHARA_IPG_GATE>; > + clock-names = "ipg", "ahb"; > + }; > + }; > > - port@2 { > - reg = <2>; > - }; > - }; > + ocram: sram@f8000000 { > + compatible = "mmio-sram"; > + reg = <0xf8000000 0x20000>; > + clocks = <&clks IMX5_CLK_OCRAM>; > }; > }; > }; Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
pgpGYz483kJeG.pgp
Description: OpenPGP digital signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
