On 09.08.19 06:15, Peng Fan wrote:
> Add board and SoC dts
> Add ddr training code
> support SD/MMC/GPIO/PINCTRL/UART
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/imx8mm-evk-u-boot.dtsi | 92 ++
> arch/arm/dts/imx8mm-evk.dts | 235 ++++
> arch/arm/mach-imx/imx8m/Kconfig | 7 +
> board/freescale/imx8mm_evk/Kconfig | 12 +
> board/freescale/imx8mm_evk/MAINTAINERS | 6 +
> board/freescale/imx8mm_evk/Makefile | 12 +
> board/freescale/imx8mm_evk/imx8mm_evk.c | 90 ++
> board/freescale/imx8mm_evk/lpddr4_timing.c | 1980
> ++++++++++++++++++++++++++++
> board/freescale/imx8mm_evk/spl.c | 102 ++
> configs/imx8mm_evk_defconfig | 70 +
> include/configs/imx8mm_evk.h | 164 +++
> 12 files changed, 2772 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx8mm-evk.dts
> create mode 100644 board/freescale/imx8mm_evk/Kconfig
> create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
> create mode 100644 board/freescale/imx8mm_evk/Makefile
> create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
> create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
> create mode 100644 board/freescale/imx8mm_evk/spl.c
> create mode 100644 configs/imx8mm_evk_defconfig
> create mode 100644 include/configs/imx8mm_evk.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ad4d2357bb..f7b674873f 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -622,7 +622,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
> fsl-imx8qxp-colibri.dtb \
> fsl-imx8qxp-mek.dtb
>
> -dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
> +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
> + imx8mm-evk.dtb
>
> dtb-$(CONFIG_RCAR_GEN2) += \
> r8a7790-lager-u-boot.dtb \
> diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> new file mode 100644
> index 0000000000..1095d36e31
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +&{/soc} {
> + u-boot,dm-pre-reloc;
> + u-boot,dm-spl;
> +};
> +
> +&clk {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&osc_24m {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&aips1 {
> + u-boot,dm-spl;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&aips2 {
> + u-boot,dm-spl;
> +};
> +
> +&aips3 {
> + u-boot,dm-spl;
> +};
> +
> +&iomuxc {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_reg_usdhc2_vmmc {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_uart2 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2_gpio {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc3 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> + u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> + u-boot,dm-spl;
> +};
> +
> +&uart2 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> + u-boot,dm-spl;
> +};
> +
> +&usdhc3 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
> new file mode 100644
> index 0000000000..2d5d89475b
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-evk.dts
> @@ -0,0 +1,235 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mm.dtsi"
> +
> +/ {
> + model = "FSL i.MX8MM EVK board";
> + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_led>;
> +
> + status {
> + label = "status";
> + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + at803x,led-act-blind-workaround;
> + at803x,eee-okay;
> + at803x,vddio-1p8v;
> + };
> + };
> +};
> +
> +&uart2 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + vmmc-supply = <®_usdhc2_vmmc>;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
> + >;
> + };
> +
> + pinctrl_gpio_led: gpioledgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> + >;
> + };
> +
> + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
> + >;
> + };
> +
> + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
> + >;
> + };
> +
> + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index 35c978e863..f520075875 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
> select IMX8MQ
> select IMX8M_LPDDR4
>
> +config TARGET_IMX8MM_EVK
> + bool "imx8mm LPDDR4 EVK board"
> + select IMX8MM
> + select SUPPORT_SPL
> + select IMX8M_LPDDR4
> +
> endchoice
>
> source "board/freescale/imx8mq_evk/Kconfig"
> +source "board/freescale/imx8mm_evk/Kconfig"
>
> endif
> diff --git a/board/freescale/imx8mm_evk/Kconfig
> b/board/freescale/imx8mm_evk/Kconfig
> new file mode 100644
> index 0000000000..299691a619
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_IMX8MM_EVK
> +
> +config SYS_BOARD
> + default "imx8mm_evk"
> +
> +config SYS_VENDOR
> + default "freescale"
> +
> +config SYS_CONFIG_NAME
> + default "imx8mm_evk"
> +
> +endif
> diff --git a/board/freescale/imx8mm_evk/MAINTAINERS
> b/board/freescale/imx8mm_evk/MAINTAINERS
> new file mode 100644
> index 0000000000..b031bb0674
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/MAINTAINERS
> @@ -0,0 +1,6 @@
> +i.MX8MM EVK BOARD
> +M: Peng Fan <peng....@nxp.com>
> +S: Maintained
> +F: board/freescale/imx8mm_evk/
> +F: include/configs/imx8mm_evk.h
> +F: configs/imx8mm_evk_defconfig
> diff --git a/board/freescale/imx8mm_evk/Makefile
> b/board/freescale/imx8mm_evk/Makefile
> new file mode 100644
> index 0000000000..1db7b62caf
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright 2018 NXP
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += imx8mm_evk.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> +endif
> diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c
> b/board/freescale/imx8mm_evk/imx8mm_evk.c
> new file mode 100644
> index 0000000000..1ea7b7f1e9
> --- /dev/null
> +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/arch/clock.h>
> +#include <spl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE |
> PAD_CTL_PE)
> +
> +static iomux_v3_cfg_t const uart_pads[] = {
> + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +int board_early_init_f(void)
> +{
> + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> + set_wdog_reset(wdog);
> +
> + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_POSTCLK_INIT
> +int board_postclk_init(void)
> +{
> + /* TODO */
> + return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> + /* rom_pointer[1] contains the size of TEE occupies */
> + if (rom_pointer[1])
> + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
> + else
The above case should be guarded with "#ifdef CONFIG_OPTEE", because if
OPTEE is not used, rom_pointer[1] does not always seem to be zero.
> + gd->ram_size = PHYS_SDRAM_SIZE;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> + return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno - 1;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + env_set("board_name", "EVK");
> + env_set("board_rev", "iMX8MM");
> +#endif
> + return 0;
> +}
[...]
> diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
> new file mode 100644
> index 0000000000..dd6f562166
> --- /dev/null
> +++ b/configs/imx8mm_evk_defconfig
> @@ -0,0 +1,70 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x10000
> +CONFIG_TARGET_IMX8MM_EVK=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
For my custom i.MX8MM board I also use mkimage_fit_atf.sh, but I have
done three modifications and I'm wondering how you are using the
unmodified version.
1. It sets ATF_LOAD_ADDR="0x910000", but in imx-atf the BL31_BASE for
i.MX8MM is set to 0x920000. How to handle this mismatch for i.MX8M and
i.MX8MM?
2. For the 'images' section of the its file, I added 'os = "u-boot";' to
the 'uboot@1' section and "os = 'arm-trusted-firmware";' to the 'atf@1'
section. Without this SPL does not detect the binaries from the FIT
image correctly.
3. In the 'config' section of the its file, I swapped the atf and uboot
entries, so the atf binary is loaded as "firmware" and the u-boot binary
as "loadable". Together with the change above (2) this leads to SPL code
using the correct boot path as inteded by the code.
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL_TEXT_BASE=0x7E1000
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMX8MM=y
> +CONFIG_CLK_IMX8MM=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_DM_MMC=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_PHYLIB=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_MXC_UART=y
> +CONFIG_DM_THERMAL=y
> diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
> new file mode 100644
> index 0000000000..cc63c44782
> --- /dev/null
> +++ b/include/configs/imx8mm_evk.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef __IMX8MM_EVK_H
> +#define __IMX8MM_EVK_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE (148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN SZ_512K
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SYS_UBOOT_BASE \
> + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
> +
> +#ifdef CONFIG_SPL_BUILD
> +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_POWER_SUPPORT
> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_STACK 0x91fff0
> +#define CONFIG_SPL_BSS_START_ADDR 0x00910000
Nitpick: Remove the leading zeros from this address.
> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> +#define CONFIG_MALLOC_F_ADDR 0x930000
> +/* For RAW image gives a error info not panic */
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#endif
> +
> +#define CONFIG_REMAKE_ELF
> +
> +#define CONFIG_BOARD_POSTCLK_INIT
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "script=boot.scr\0" \
> + "image=Image\0" \
> + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
> + "fdt_addr=0x43000000\0" \
> + "fdt_high=0xffffffffffffffff\0" \
> + "boot_fdt=try\0" \
> + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "initrd_addr=0x43800000\0" \
> + "initrd_high=0xffffffffffffffff\0" \
> + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> + "mmcautodetect=yes\0" \
> + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
> + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${script};\0" \
> + "bootscript=echo Running bootscript from mmc ...; " \
> + "source\0" \
> + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "mmcboot=echo Booting from mmc ...; " \
> + "run mmcargs; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if run loadfdt; then " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "echo wait for boot; " \
> + "fi;\0" \
> + "netargs=setenv bootargs console=${console} " \
> + "root=/dev/nfs " \
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> + "netboot=echo Booting from net ...; " \
> + "run netargs; " \
> + "if test ${ip_dyn} = yes; then " \
> + "setenv get_cmd dhcp; " \
> + "else " \
> + "setenv get_cmd tftp; " \
> + "fi; " \
> + "${get_cmd} ${loadaddr} ${image}; " \
> + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "booti ${loadaddr} - ${fdt_addr}; " \
> + "else " \
> + "echo WARN: Cannot load the DT; " \
> + "fi; " \
> + "else " \
> + "booti; " \
> + "fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> + "mmc dev ${mmcdev}; if mmc rescan; then " \
> + "if run loadbootscript; then " \
> + "run bootscript; " \
> + "else " \
> + "if run loadimage; then " \
> + "run mmcboot; " \
> + "else run netboot; " \
> + "fi; " \
> + "fi; " \
> + "else booti ${loadaddr} - ${fdt_addr}; fi"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR 0x40480000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#if defined(CONFIG_ENV_IS_IN_MMC)
> +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
> +#endif
> +#define CONFIG_ENV_SIZE 0x1000
> +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
> +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN SZ_32M
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
> +
> +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START +
> (PHYS_SDRAM_SIZE >> 1))
> +
> +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_CBSIZE 2048
> +#define CONFIG_SYS_MAXARGS 64
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* USDHC */
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM 2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
> +
> +#define CONFIG_SYS_I2C_SPEED 100000
> +
> +#endif
>
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