On Thu, Nov 14, 2019 at 02:44:24PM +0530, Vignesh Raghavendra wrote: > Flush caches when pushing an element to ring and invalidate caches when > popping an element from ring in Exposed Ring mode. Otherwise DMA > transfers don't work properly in R5 SPL (with caches enabled) where the > core is not in coherency domain. > > Reviewed-by: Grygorii Strashko <grygorii.stras...@ti.com> > Signed-off-by: Vignesh Raghavendra <vigne...@ti.com>
Reviewed-by: Tom Rini <tr...@konsulko.com> -- Tom
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