The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet.
Signed-off-by: Marek Vasut <ma...@denx.de> Cc: Ley Foon Tan <ley.foon....@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> --- include/configs/socfpga_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..8c5dcfa57c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -98,8 +98,10 @@ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif /* * L4 Watchdog -- 2.25.0