On Sat, Feb 15, 2020 at 10:40 PM Marek Vasut <ma...@denx.de> wrote: > > On 2/15/20 8:39 PM, Simon Goldschmidt wrote: > > Am 15.02.2020 um 15:02 schrieb Marek Vasut: > >> The default timer rate may be different than 25 MHz, permit overriding > >> the default rate in board configuration file. Ultimatelly, this should > >> be properly handled by a clock driver, however that is not available > >> on Gen5 yet. > > > > Sigh, yes, I still haven't found the time to fight those size problems I > > have... :-( > > > >> > >> Signed-off-by: Marek Vasut <ma...@denx.de> > >> Cc: Ley Foon Tan <ley.foon....@intel.com> > >> Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> > >> --- > >> include/configs/socfpga_common.h | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/include/configs/socfpga_common.h > >> b/include/configs/socfpga_common.h > >> index 8d10469e7c..8c5dcfa57c 100644 > >> --- a/include/configs/socfpga_common.h > >> +++ b/include/configs/socfpga_common.h > >> @@ -98,8 +98,10 @@ > > > > Just above this line, there's this comment: "This timer uses eosc1, > > whose clock frequency is fixed at any condition". > > > > While I'm ok with the change below, it does look a bit funny to make > > this overriable if it's "fixed at any condition". Could you elaborate on > > this? Do we need to change the comment? > > The comment is probably wrong, since you can connect the SoCFPGA > external oscillator input to any applicable xtal ?
Right. Could you delete that comment then with this patch to prevent confusion? Regards, Simon